JPH05282205A - Information processor - Google Patents

Abstract

PURPOSE:To shorten a time required for the processing of the dummy read of a memory or a register on a bus in order to make a write buffer empty, when it is necessary to complete a write operation from a CPU. CONSTITUTION:A high speed register 1 for the dummy read is provided on a bus 2, and at the time of the dummy read, an access to the high speed register 1 for the dummy read is performed from a CPU 3 through the bus 2. The high speed register 1 receives an instruction and immediately ends an operation, so that the processing can be attained in a short time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a write buffer, and more particularly, to an information processing apparatus which speeds up processing when it is desired to maintain consistency between a write buffer and a memory.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a CPU unit 6 including a CPU 3, a cache 4 and a read / write buffer 5, a register group 7, a memory 8 and an I / O 9 are connected by a bus 2 as an information processing apparatus. There is something connected.

In this information processing apparatus, the dummy read method for emptying the write buffer utilizes the property that it is necessary to wait until the write buffer becomes empty in order to perform non-cache access. C such as system status display and synchronization with external interface
When it was necessary to complete the write operation from the PU, the memory or register in the non-cache area was dummy-read and the write buffer was emptied in order to ensure consistency with the memory.

Dummy read to the non-cache area for emptying the write buffer has been accessed through the route shown by the dotted line in FIG. This took several clocks.

[0005]

However, in the above information processing apparatus, the memory or register is limited in speed and the result is not necessary because it is merely a dummy read, but the write buffer is empty. There was a drawback that you had to wait until the result came after.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an information processing apparatus capable of performing a dummy read for emptying a write buffer at high speed.

[0007]

In order to achieve the above object, an information processing apparatus of the present invention connects a CPU unit consisting of a CPU, a cache and a write buffer, a register group, a memory and an I / O with a bus, and a CP. Information processing having means for emptying the write buffer in order to ensure consistency between the write buffer and the memory when it is necessary to complete the write operation from the CPU such as system status display and synchronization with an external interface during bus read In the device, a high-speed dummy register for performing a dummy read for emptying the write buffer at a high speed is provided on the bus.

[0008]

According to the information processing apparatus having the above structure, the high-speed register for dummy read is provided on the bus to reduce the waiting time during dummy read.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an information processing apparatus according to an embodiment of the present invention, which is equipped with a dummy read high speed register.

In the figure, 6 is a CPU unit 6, and C
It comprises a PU 3, a cache 4, and a read / write buffer 5. The CPU unit 6 includes a group of registers 7,
It is connected to the main memory 8 and I / O 9.

In addition, this information processing apparatus, when it is necessary to complete the write operation from the CPU 3 such as the system status display and the synchronization with the external interface at the time of reading the CP bus, the consistency between the write buffer 5 and the memory 8 is satisfied. The write buffer 5 is emptied in order to obtain

Numeral 1 is a high-speed dummy read register provided on the bus 2 for performing a high-speed dummy read for emptying the write buffer 5 and is accessed by the CPU 3.

Therefore, according to the information processing apparatus of this embodiment, the non-cache area access for completing the write operation of the CPU is as shown by the dotted line path in FIG. The read instruction issued from the CPU 1 to the register 1 goes out to the bus 2 without accessing the cache 4,
Before that, the write buffer 5 must be empty. When the write buffer becomes empty, the read instruction is output on the bus 2, and the register 1 ends the processing immediately upon receiving the instruction.

That is, when it is necessary to complete the write operation from the CPU and when the memory or register on the bus is dummy read to empty the write buffer,
The dummy read high speed register 1 is accessed from the CPU 3 via the bus 2.

As a result, the register 7 and the memory 8 are conventionally used.
Although they are accessing the memory, they take a long time to operate because they have to wait for the operation to end and the result to be returned even though it is a dummy read. On the other hand, the high-speed register 1 of the present embodiment ends its operation immediately upon receiving an instruction, so that the processing can be performed in a short time.

[0016]

As described above, according to the information processing apparatus of the present invention, by providing a high-speed register that can be accessed as a non-cache area on the bus, the write buffer and the memory can be matched. The effect is that a dummy read for emptying can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an information processing apparatus according to a conventional example.

[Explanation of symbols]

 1 high-speed register for dummy read 2 memory bus 3 CPU 4 cache 5 read / write buffer 6 CPU section 7 register group 8 memory 9 I / O

Claims (1)

[Claims] 1. A CPU unit comprising a CPU, a cache and a write buffer, a register group, a memory and an I / O.
A CPU that connects O with a bus, displays the system status when reading the CP bus, and synchronizes with an external interface
In the information processing apparatus having a means for emptying the write buffer in order to make the write buffer and the memory consistent with each other when the write operation from the memory is required to be completed, dummy read for emptying the write buffer is performed at high speed. An information processing device, characterized in that a high-speed dummy register is provided on the bus.