JPS63249240A - Data transfer control system in cache memory system - Google Patents

Abstract

PURPOSE:To improve performance based on rapid access by selecting and transferring corresponding data when a processor outputs a memory reading request during nibble operation and data transferring to a cache memory. CONSTITUTION:The title system is provided with a transfer control means 40 for transferring data to be transferred in the 1st time out of data to be transferred 4 times by nibbling operation at the time of detecting a cache mishit to a processor 10, selecting corresponding data 51 out of data to be transferred in the 2nd time and after and transferring the selected data 51. Namely, a device having a 32-bit processor and a 16-bit main memory transfers 1st and 2nd transfer data continuously to the processor 10. When the processor and the main memory have the same bit width, the 2nd address data and after out of transfer data are compared with address data outputted based on a memory reading signal and data outputted at the time of coincidence of data are transferred. Consequently, system performance due to rapid access can be obtained.

Description

[Detailed Description of the Invention] [Summary] In a cache memory system in which data is transferred from main memory to cache memory in nibble mode, when a cache miss is detected, the first data in nibble mode is transferred to the processor. In addition, when a memory read request is output during a nibble operation, a data transfer control method selects corresponding data from the second and subsequent transfer data and transfers it to the processor.

[Industrial application field]

The present invention relates to an improvement in a data transfer control method in a cache memory system.

In a data processing device in which a cache memory is placed between a processor and a main memory in nibble mode, when a cache miss is detected, data is transferred from the main memory to the cache memory in nibble mode, but the nibble operation ends. The processor's memory read request is made to wait until

This hinders high-speed control, and there is a need for a data transfer control method that solves this problem.

[Conventional technology]

FIG. 6 is an explanatory diagram of a conventional data transfer control system, in which (1) is a block diagram of a data processing device, and (II) is a system configuration diagram with different transfer bus widths.

In Figure 6 (1), 1 is a processor whose address space is IMB (AD19 to 0), and 2 is a dynamic random access memory (DRAM).
), which is equipped with a counter 9 for nibble operation, 3 is a timing circuit that generates a timing signal for transfer control, and 4 is a cache memory, which includes a cache control unit 5.
and a data memory 6.

Hereinafter, in order to facilitate understanding of the present invention, an outline of the operation of each part will be explained based on the above configuration.

(Cache operation) (1) When data is transferred from the main memory 2 to the data memory 6, the address data corresponding to the data is stored in the memory (not shown) of the cache control unit 5.
Address data 8012 to 19 are stored using addresses 3 to 11 (AD is an address bit), and the valid bit V is set to "1".

(2) When processor 1 outputs address data to perform memory read access, AD3 to AD11
addresses the memory of the cache control unit 5, and its output and AD12 to AD19 are compared by the comparison unit 7.

(3) If the comparison results in a match and V=“l” (by the AND circuit 8), a hit signal old T indicating that the corresponding data exists in the data memory 6 is output.

The cache control unit 5 is composed of four sets of control blocks (4WAY) that perform the above operations, and the hit signal output from each control block is encoded into 2 bits, and the 2 bits and MDI-11 (word access) are encoded into 2 bits. The data memory 6 is accessed using this as an address.

As a result of the above, the predetermined data exists in the data memory 6 (
If the cache memory 4 is present, the processor 1 can read data from the cache memory 4, and can read data at high speed.

(Cache miss hint control operation) When a cache miss hint is detected in all control blocks in the above operation (output of OR circuit 91), transfer from main memory 2 to cache memory 4 is performed based on the output address data. The operation is performed and at the same time processor 1 reads the data.

Figures 6(n) and 7(I) show the above operations in the nibble mode, where the main memory 2 is read four times, and the processor 1 is read in the first read operation. memory 2
The data 50 output from is read and the memory read access is completed.

Note that the main memory 2 has rows (corresponding to the upper bits of ROW i address data) and columns (COLUMN;
Lower bit) DR where 1 bit is accessed by address
AM elements are provided for the data bus width, and by applying a CAS (column address strobe) signal following a RAS (row address strobe) signal, the column address is incremented by the counter 9, and each DRAM element is incremented by 4 bits. read/write continuously).

[Problem that the invention seeks to solve]

When a cache miss pit is detected and data is transferred from the main memory 2 to the cache memory 4 in nibble mode, the first data is transferred to the processor l, but the second
During the period TW to the fourth transfer operation [FIG. 7 (■)], the next access cannot be performed, which hinders speeding up.

In addition, a 32-bit processor configured to read 16-bit data and then output a 16-bit read request has a 16-bit main memory, 10 control However, in the data transfer method described above, the next 16-bit read access must wait until the nibble operation is completed.

An object of the present invention is to provide a data transfer control method in a cache memory system that solves the above problems.

Means for Solving Problem C] For the above purpose, the data transfer control method in the cache memory system of the present invention, as shown in FIG. Of the data transferred four times, the data transferred the first time (50)
is transferred to the processor (10), and when a memory read request is output from the processor during the nibble operation, the corresponding data (51) is selected from the data transferred from the second time onwards and is sent to the processor (10). 10) is provided with a transfer control means (40) for transferring the data.

[Effect]

There are the following transfer controls for selecting corresponding data from data being transferred in nibble mode and transferring it to the processor.

(1) In a device having a 32-bit processor and a 16-bit main memory, the first transfer data and the second transfer data are transferred to the processor 10 consecutively.

(2) If the processor and main memory have the same bit width,
The second and subsequent address data of the transfer data is compared with the address data output in response to the memory read request, and when they match, the output data is transferred to the processor.

As described above, corresponding data can be selected and transferred in response to a memory read request output during a nibble operation.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

[First embodiment] Fig. 2 is a block diagram of the first embodiment, Fig. 3 is a timing circuit block diagram of the first embodiment, and Fig. 4 is an operation time chart of the first embodiment. be.

This embodiment has a processor 10 (FIG. 2) with both an address space and a data width of 32 bits, a cache memory 12 with a 32-bit data width, and a main memory 1 with a 16-bit data width.
3 shows an example of data transfer control in a cache memory system configured with 3 and 3, and shows an example of transferring first and second transfer data in nibble mode to the processor 10.

In FIG. 2, reference numeral 11 denotes a timing circuit, and when the processor 10 performs memory read access and a cache miss is detected, the processor 10. A transmitter TR 14 controls data transfer by outputting timing signals to the main memory 13 and the cache memory 12, respectively (corresponding to the transfer control means 40), and a 16-bit data bus to which the main memory 13 is connected and a processor 0 and the 32-bit data bus connected to the processor 0.0 to perform data alignment and opening/closing control. Cash memo January 2. Each of the main memories 13 has the bit width described above.

Hereinafter, details of the timing circuit and operation timing will be explained in detail with reference to FIGS. 3 and 4.

In addition, among the signal names, pHxx is a timing circuit! Signal names used in 18, * and one sign are negative logic,
Δ represents an AND symbol, and FIG. 4 is a time chart at the time of a cache miss.

Read data access■ (1st data read) +11 *ADS is a bus request signal output from processor 0 along with address data AD31-0.
After bus permission, memory read signal *MREAD is output, and PH7A is sent (1'') to flip-flop JKFF21 at J-.

OFF 24 is a flip-flop that delays the input signal by one clock, and *PI7Al is output after one clock has elapsed.

(2) PH7A△*PH781 (=*O
E) - When “1” (AND 29) is output to the cache memory 12, a cache check is performed, and a miss is detected. and set in JKFP26.

(31P117 has main memory 13 to cache memory 1
This means that the nibble mode has been activated in order to transfer data to 2, and is output as the *RAS signal via the inverter 33.

(4) *PH7CAPH7CI = *R
1
The first 6-bit data (FIG. 4) (data 50 transferred for the first time) is read.

The above read data access ■ is a 32-bit access, so when *B516 = "O" is notified, the remaining 1
In order to read 6-bit data, the bus request signal *ADS is outputted again, and read data access (2) is activated.

Read data access ■ (second data read) (5) 1 to PH7 is △ to PH7 (PH7CAPH
7C1') = "1" condition (AND 34) JKF
It is set to F25, and in read data access ■, P
P) 1 on H7KAPH7 under the condition of 1△ADS = “1”
7c is set (PH7C board data access ■
(reset at P117CI), the second write operation to the cache memo January 2 and data transfer to the processor 10 (corresponding data 51) are executed in parallel.

In the state where 1 = "1" in PH7 (*1 = 60" in PH7), even if ADS = "1" is output, it will be kept waiting.

(6) PHA4 and PHA5 are *CAS signals and timing signals for creating a *casing pulse *ridge.

In FIG. 3, the counter 27 outputs four sets of CAS signals and generates a CS signal for selecting the address data memory 12.

Although not shown, the address of the cache memory 12 is controlled by an address latch circuit which latches the address data output from the processor 10 and whose lower two bits are constituted by a counter and which increments each time a transfer is made.

As described above, when a cache miss is detected, 2W of data can be continuously transferred to the processor based on the timing signal.

[Second Embodiment] In the second embodiment, in a system where both the processor and the main memory have the same bit width, when the processor outputs a bus access request during nibble operation, the address of the data being transferred and the processor output This example shows an example in which the data being transferred is transferred to the processor when the address is compared with the address that is being transferred.

FIG. 5 is a block diagram of the second embodiment, in which 35 is a gate that opens and closes the address bus, and 36 is the aforementioned address latch, which latches address data 61 when a cache miss is output by the processor≠. (Actually, the output immediately before the gate 35 is latched) and the comparator 37 controls the address of the cache memory by stepping every time data is transferred in the nibble mode.

When the processor performs a memory read access and a cache miss occurs, the first data in nibble mode is transferred to the processor tray together with the cache memory.
Subsequently, when a bus access request is output, the simultaneously output address data 60 (closed by the gate 35) is compared with the address data 61 (output of the address latch 36) of the data being transferred, and if they match. At this time, the timing circuit 38 outputs a timing signal such as a READY signal to the processor U, and the data being transferred is transferred to the processor station.

Normally, processor accesses are in ascending order of addresses and often match the address of the nibble operation, so the proportion of waiting until the end of the nibble operation is reduced, and performance improvement can be expected.

〔Effect of the invention〕

As explained above, in the present invention, when the processor outputs a memory read request during nibble operation and transfer to cache memory, the corresponding data is selected and transferred, so the performance improvement effect due to high-speed access is It is extremely large.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of the first embodiment, Fig. 3 is a timing circuit block diagram of the first embodiment, and Fig. 4 is the operation of the first embodiment. FIG. 5 is a block diagram of the second embodiment, FIG. 6 is an explanatory diagram of a conventional data transfer system, (I) is a block diagram of a data processing device, and FIG. 7 is an explanatory diagram of problems. , (1) is a transfer operation flowchart, and (II) is a system configuration diagram with different data bus widths. In the figure, 10 is a processor, 11 is a timing circuit, I2 is a cache memory, 13 is a main memory, and 20.21, 22.23.25.26 are Jk flip-flops JKFF. 24 is a D-type flip-flop OFF. 27 is a counter, 28 is an address decoder, 29.30.31, 32.34 is an ND circuit, 33 is an inverter, 35 is a gate, 36 is an address latch, 37 is a comparison section, 38 is a timing circuit, 50 is a nibble mode Data transferred at the first time, 51
40 is the corresponding data for the second and subsequent times, and 40 is the transfer control means. Figure 1: Block diagram of the first embodiment Figure 2: Timing circuit block diagram of the first embodiment *0[! 1-
" *uE -m-■"
Figure 4 Block diagram of the second embodiment Figure 5 (1) Data processing device block diagram 1 - Add 3W 4W (II) Transfer complement time Chart diagram Conventional data transfer control method explanatory diagram Figure 6

Claims (1)

[Claims] A processor (10), a cache memory (12),
A data transfer control method in a cache memory system comprising a main memory (13) accessed in nibble mode, the data being transferred first among the data transferred in the nibble operation when a cache miss is detected ( 50
) to the processor (10), and when a memory read request is output from the processor during the nibble operation, the corresponding data (51) is selected from the data transferred from the second time onward and the processor A transfer control means (40) is provided to transfer the data to the cache memory (12), and when a memory read request occurs during transfer to the cache memory (12) by nibble operation, the corresponding data is selected from the data being transferred, and the (10) A data transfer control method in a cache memory system characterized by transferring data.