JPH0528770A - Multiport memory circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction in the same reading cycle period by searching the logical sum of the output of an output data holding circuit with a reading request signal, and outputting the data of a shared memory to an outside circuit only at the time of a reading request. CONSTITUTION:When an address A comes first so as to be established in order to operate a reading operation, and an address B comes next so as to be established in order to operate the reading operation, storage information in a shared memory cell 11 is latched by an output data holding circuit 14a. Then, the logical sum of the output of a circuit 14a with the reading request signal is searched, and the data are outputted to the outside circuit only at the time of the reading request. At that time, the data of a first-come reading port are left to be latched by the circuit 14a until the neat address is inputted, and the data are not affected by the change of the storage information. Then, a writing operation from the next-come side port of the address can be attained, and the transition of the reading data of the first-come side port in the same reading cycle period can be prevented. Thus, the malfunction can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport memory circuit, and more particularly to a circuit configuration capable of performing writing and reading independently and asynchronously from a plurality of ports.

[0002]

2. Description of the Related Art A conventional multiport memory circuit is configured to have a matrix-shaped shared memory cell block, a row decoder for selecting the memory cell block, and a column decoder for each port. Port M
According to a command from the PU, the information in the shared memory cell at the intersection of the selected row and column is read out to the output, and the input data is written to the shared memory.

FIG. 6 is a schematic configuration diagram of the most common two-port memory circuit in the conventional multi-port memory circuits. This will be described as an example. In the figure, reference numeral 41 denotes a shared memory, which is configured to be accessible from A, B and two ports, respectively. Specifically, the address buffer A43, the row decoder A44, the column decoder A45, I
A port block (addition of symbol A) composed of / O buffer A42, address buffer B47, row decoder B4
The shared memory cell array 41 is independently and asynchronously accessed via the B port block (adding the symbol B) formed of the column decoder B49, the column decoder B49, and the I / O buffer B46. Further, 50 is an access port arbitration circuit when the same address conflict is selected in the shared memory cell array 41 which is required only for the multiport memory.

Next, the operation will be described. FIG. 7 is a block diagram of a conventional multiprocessor system of a two-port memory circuit. As shown in the figure, the A and B access ports have independent bus lines A and B, respectively, and they are individually connected via the bus lines A and B. It is connected to the corresponding MPU _A 51 and MPU _B 52, and accesses the shared memory cell 53 in response to an instruction from the corresponding MPU. In this case, the MPU _A 51 and MPU _B 52 connected to the respective ports A and B independently and asynchronously arbitrarily select the address of the shared memory 53, and read and write data to the selected address from each port. A write operation is performed.

Next, the operation of the shared memory 53 will be described. The row decoder A44 and the column decoder A45 are the M
The address input from PU _A is input via the address buffer A 43, and the intersection of the row and the column selected by each is selected as the A port accessible memory cell in the shared memory cell array 41. The A-port accessible memory cell responds to a read or write command from the MPU _A , outputs the storage information in the memory cell to the I / O buffer A42 in the case of read, and the I / O buffer in the case of write. The information of A42 is stored in the memory cell.

On the contrary, the row decoder B48 and the column decoder B49 input the address input from the MPU _B through the address buffer B47, and the intersection of the row and the column selected by them is stored in the shared memory cell array 41. Select as a B-port accessible memory cell. The B port accessible memory cell responds to the read and write commands from the MPU _B , outputs the storage information in the memory cell to the I / O buffer B46 in the case of read, and the I / O buffer in the case of write. 46 information is stored in the memory cell.

The operation waveforms when the same address is selected in the shared memory cell array 41 will be described. Since the A and B ports access the shared memory cell array 41 asynchronously, there are two possible cases for the same address in the shared memory cell array 41: A port access first arrival and B port access first arrival. For portability, the A port access first arrival will be described here.

FIG. 4 is a diagram showing operation waveforms of a conventional two-port memory circuit. In the figure, address A determines first arrival, read operation is performed, address B determines last arrival, and write operation is performed. The case will be described as an operation example. In this case, I / O _A (D _out ) on the first A port side
It is possible that the read data may transition during the same read cycle period due to the I / O _B (D _in ) write data on the late arrival B port side.

In order to avoid such an operational problem, an access port arbitration circuit 50 is usually added to the 2-port memory as shown in FIG. 6 in order to select the same address in the shared memory cell array. ing. FIG. 5 shows A
FIG. 6 is a diagram showing an access arbitration function of an access port arbitration circuit 50 in the case of first-arrival of a port.

The access port arbitration circuit 50 uses the MP
U _A, an address input from the MPU _B is the same, with giving priority port access to the shared memory cell array 41 acts only upon the competitive selection, either port, with respect to non-priority ports The / Busy signal is output to "L" to inform the MPU of the corresponding port that it has no priority. The MPU to which the / Busy signal "L" is input keeps the operation in the wait state until the address conflict of both ports is released, and stops the MPU access (FIG. 5).

[0011]

Since the conventional 2-port memory circuit is configured as described above, the same address in the shared memory cell array is selected from both A and B ports,
For example, when the mode of each port is set to read operation for the first-arrival port and write operation for the second-arrival port, output data may transit during the same cycle period. Further, when the same address in the shared memory cell array is selected from both the A and B ports, and the mode of each port is set to the write operation for both the first arrival port and the second arrival port, the storage data in the shared memory cell array is There were also uncertain operational problems.

Furthermore, in order to solve the above problems, the conventional 2-port memory circuit must have an access port arbitration circuit which operates only when the same address in the shared memory cell array is selected from both A and B ports. However, since the access port arbitration circuit performs the access priority determination only by comparing the timings of the address confirmation regardless of the operation mode from each port, there is waste in the / Busy signal output for the access permission, There are problems such as waste of MPU operation.

The present invention has been made to solve the above problems, and when the same address in the shared memory cell array is selected from both A and B ports, the read data of the first arrival port is the last arrival data. It is an object of the present invention to obtain a multi-port memory circuit in which the write data of a port does not change during the same read cycle.

In addition, / B by the access port arbitration circuit when the same address in the shared memory cell array is selected
It is possible to reduce the output of the busy signal "L" to 1/2 of that of the conventional one, and to improve the operating rate of the MPU that responds to the output to double the conventional rate.

[0015]

In a multiport memory device according to the present invention, read data from a shared memory is used as a data input before the data output of each port, and the confirmation of the address input of the corresponding access port is detected. An output data holding circuit that uses the output of the circuit as a clock input, and the output of the data holding circuit is the read request signal /
The logical sum is obtained with OE, and the read data is output to an external circuit only when a read request is made.

Also, the output of the access port arbitration circuit,
The OR of the write request signal / WE on the reverse access port side of each access port is ORed, and when the write request signal of the reverse access port is input, the determination result of the access port arbitration circuit is output to the external MPU as / Busy output. To do.

[0017]

The multiport memory circuit according to the present invention is
Since the data holding circuit is provided in the output stage of each port, this stored information in the memory is temporarily held at each transition of the address input of each port regardless of the setting of the access mode, and the access port requests reading. If the same address in the shared memory cell array is selected from each port, the read data of the first arrival port will be the same as the write data of the second arrival port even if the same address is selected from each port. No transition occurs during the read cycle.

Further, the output of the access port arbitration circuit,
By taking the OR logic with the reverse access port write request signal, only when the access request is late and the reverse port (first arrival port) is the write operation request,
Access port arbitration result / Busy output terminal /
By outputting "L" of the Busy signal, / Bu
The output of the sy signal “L” can be halved as compared with the conventional one, and the operating rate of the MPU which responds to it can be doubled as compared with the conventional one.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. FIG. 1 is a block diagram of a 2-port memory circuit according to an embodiment of the present invention. In the figure, 11 is a shared memory cell capable of independent and asynchronous read / write operations from both A and B ports, 12 is an address A, An access port arbitration circuit that compares the address B inputs and operates only when the same address of the shared memory cell is selected, and 13a and 13b are address confirmation detection circuits that detect that the address setting of each port has been confirmed. Data holding circuits 14a, 14
It is connected to the clock T of b. 14a and 14b use the read data from the shared memory as the data input, and
It is an output data holding circuit which operates by using the address confirmation detection circuits a and 13b as a clock input. 15a, 15b
Is a logical sum gate of the output of the output data holding circuits 14a and 14b of each port and the read request signal / OE. 1
Reference numerals 6a and 16b denote OR gates of the outputs of the access port arbitration circuit 12 and the write request signal / WE signal of the reverse access port.

Next, the operation of the embodiment of the present invention will be described. FIG. 2 shows operation waveforms of the 2-port memory circuit shown in FIG. Like the conventional example, access arrival of both A and B ports to the same address in the shared memory cell is conceivable, but here, for simplification, only A port access arrival will be described.

In FIG. 1, the address A is confirmed first-come-first-served basis,
When the read operation is performed, the address B is finalized and the write operation is performed, the stored information in the same selected address in the shared memory cell 11 is immediately stored in the output data holding circuit 14a when the A port address is finalized. It is latched (at the time of FIG. 2). The latched data is the read signal /
OE _A becomes “L”, and output to I / O _A (D _out ) is started for the first time (at the time of FIG. 2).

At this time, the data of the first-arrival read port is
Until the address of the next first-arrival port is input (until the address transitions), it remains latched in the above-mentioned data holding circuit 14a, so the stored information of the address in the shared memory cell 11 may change. There is no state. Therefore, the write operation from the latter-arrival port to the address becomes possible, and the conventional problem that the read data from the first-arrival port transits during the same read cycle does not occur.

Further, with this operation, the determination result of the access port arbitration circuit 12 (later arrival), which is determined only by the address determination timing difference between the A and B ports, regardless of the mode setting from each port as in the prior art. On side port / Bu
sy “L” output) is also output only when the write signal of the first-arrival port becomes “L”. FIG. 3 is a diagram showing the arbitration function of the access port arbitration circuit according to the embodiment of the present invention when the A port arrives first. In FIG. 3, mode setting, mode access permission, and / B of each port are shown.
The relationship of the busy output is as shown here, / Busy
The output probability of the output can be halved as compared with the conventional one.

Although the two-port memory circuit has been described as a typical example in the above embodiment, the same idea can be used.
The same effect can be obtained when applied to a multi-port memory circuit having more than ports.

Further, in the above embodiment, only the multi-port memory circuit having the shared memory cell for each access port has been described.
The same effect can be obtained for the shared memory configured by the AM + gate array.

[0026]

As described above, according to the multiport memory circuit of the present invention, by providing the data holding circuit in the output stage of each port, the access mode is changed every time the address input of each port transitions. Regardless of the setting, this stored information in the memory is temporarily held, and the held data is output to the outside only when the access port is a read request. Therefore, the same data in the shared memory cell array is output from each port. Even when the address is selected, the read data of the first arrival port can be prevented from transitioning (malfunction) during the same read cycle period by the write data of the second arrival port.

Further, the output of the access port arbitration circuit,
By taking the OR logic with the reverse access port write request signal, only when the access request is late and the reverse port (first arrival port) is the write operation request,
Access port arbitration result / Busy output terminal /
By outputting "L" of the Busy signal, it becomes possible to limit the access to the late arrival side port, which is completely disabled, only when the write mode of the first arrival side port is set (1/2 of the conventional), and sharing This has the effect of improving the operating rate of the MPU itself when the same address in the memory is selected.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiport memory circuit according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of a multiport memory circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing an arbitration function of an access arbitration circuit according to an embodiment of the present invention when an A port arrives first.

FIG. 4 is an operation waveform diagram of a conventional multiport memory circuit.

FIG. 5 is a diagram showing an arbitration function of a conventional access arbitration circuit when an A port arrives first.

FIG. 6 is a schematic configuration diagram of a conventional multiport memory circuit.

FIG. 7 is a configuration diagram of a conventional multi-processor multiprocessor system.

[Explanation of symbols]

11 shared memory cells 12 Access port arbitration circuit 13a A port address confirmation detection circuit 13b B port address confirmation detection circuit 14a A port output data holding circuit 14b B port output data holding circuit 15a OR gate 15b OR gate 16a OR gate 16b OR gate

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[Procedure amendment]

[Submission date] January 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

[0017]

The multiport memory circuit according to the present invention is
By providing the data holding circuit to output the previous stage of each port, regardless of the setting of the access mode each time the address input of each port is changed, temporarily holds the stored information in the memory, the access port is a read request If the same address in the shared memory cell array is selected from each port, the read data of the first arrival port will be the same as the write data of the second arrival port even if the same address is selected from each port. No transition occurs during the read cycle.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. FIG. 1 is a block diagram of a 2-port memory circuit according to an embodiment of the present invention. In the figure, 11 is a shared memory cell capable of independent and asynchronous read / write operations from both A and B ports, 12 is an address A, An access port arbitration circuit that compares the address B inputs and operates only when the same address of the shared memory cell is selected, and 13a and 13b are address confirmation detection circuits that detect that the address setting of each port has been confirmed. Data holding circuits 14a, 14
It is connected to the clock T of b. 14a and 14b use the read data from the shared memory as the data input, and
a, an output data holding circuit which operates as a clock input the output of the address confirmation detection circuit 13b. 15a,
Reference numeral 15b designates output data holding circuits 14a and 14b for each port.
Is a logical sum gate of the output of and the read request signal / OE. 16a and 16b are OR gates of the respective outputs of the access port arbitration circuit 12 and the write request signal / WE signal of the reverse access port.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

[0026]

As described above, according to the multiport memory circuit of the present invention, by providing the data holding circuit in the output front stage of each port, the address input of each port can be achieved.
There regardless of the setting of the access mode each time transition, temporarily holds the stored information in the memory, the access port only if a read request, since so as to output the held data to the outside, each Even when the same address in the shared memory cell array is selected from the port, the read data of the first arrival port can be prevented from transitioning (malfunction) during the same read cycle by the write data of the second arrival port.

Claims (2)

[Claims] 1. A multi-port memory circuit having at least two access ports, each of which can access a shared memory, wherein the multi-port memory circuit is provided in front of data output of each port and reads from the shared memory. An output data holding circuit that uses data as a data input and detects the confirmation of the address input of each port and uses it as a clock input, and the output of the output data holding circuit is logically ORed with the read request signal and read. A multi-port memory circuit comprising an OR circuit for outputting the read data of the shared memory to an external circuit only when requested. 2. An access port arbitration circuit having an access port arbitration function that permits mode access only when the same address is selected in the shared memory, a determination output of the access port arbitration circuit, and access ports on opposite sides of each other. And a logical sum circuit that outputs the determination result of the access port arbitration circuit to an external circuit when the logical sum of the write request signal of the access port and the write request signal of the access port on the opposite side is input. The multiport memory circuit according to claim 1, wherein