JPH03231345A - Cache device - Google Patents

Abstract

PURPOSE:To perform the zero clear processing at a high speed by adding a zero clear flag of a cache block to each block tag and completing the zero clear processing just with raising a flag of the corresponding block to be zero- cleared. CONSTITUTION:The tags are stored in a block storage means 12 for each data block of a cache data storage means 10. These tags include the valid/invalid flags V of data blocks, the zero clear flags C, and the addresses ADR showing the data blocks. When a microinstruction is generated for zero clearing, the head address of a relevant block is set to a tag address register 80 and a data address register 82 respectively. Then the flag C is rewritten into '1' by a cache control part 16 when a tag bit is confirmed at a tag bit signal output part 14. Thus a zero clear processing is through. Thereafter the reading of data is suppressed into '0' by the flag C via a gate 22 together with the move-in is suppressed into '0' via a gate 20 respectively. In such a constitution, the zero clear processing is carried out at a high speed.

Description

[Detailed description of the invention]

[Table of Contents Outline Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples Effects of the Invention Cta Summary] Regarding a cache device in which cache data is zero-cleared in block units, A cache data storage means for storing a plurality of data blocks to be zero-cleared in units of a predetermined data width, the purpose of which is to provide a cache device that can zero-clear data blocks at high speed;
block tag storage means for storing, for each data block, a tag including a first flag indicating whether the data block is valid or invalid, a second flag indicating whether the data block has been cleared to zero, and an address indicating the data block; , a tag hit signal output means for outputting a tag hit signal when the first flag of the tag containing an address indicating the data block to be zero cleared indicates that the data block is valid; and zero clear flag control means for changing the second flag of the tag containing the indicated address to a state indicating zero clearing of the data block when the tag hit signal is output. [Industrial Application Field] The present invention relates to a cache device in which cache data is cleared to zero in block units. In many computer systems, a cache is introduced, which speeds up access. [Prior Art] A configuration of a conventional example is explained in FIG. Data is stored in blocks of bytes.Block tags having the configuration shown in FIG. 9 for each of these data blocks are stored in the block tag storage unit 12. It consists of a cache block valid flag (■) indicating whether the block is valid or invalid, and a tag address ADR.Here, in order to efficiently clear a wide cache area to zero, one data block in the cache data storage unit 10 is cleared to zero data. When this microinstruction is executed, data indicating the address of the start of the block is set in the tag address register 80 and the data address register 82.Then, the contents of the tag address register 80 are When a block tag is read from the tag storage section 12 using a part of the block tag, the address ADH included in the block tag and the address included in the contents of the tag address register 80 are compared at the gate 14a of the tag hit signal output section 14. In addition, the cache block valid flag ■ of the block tag read from the block tag storage section 12 is given to the gate 14b of the tag hit signal output section 14.The flag at that time indicates that the corresponding data block is valid. (V=1), the gate 14b is opened. The output of the gate 14a is applied to this gate 14b, and the connection between the address ADH on the block tag storage section 12 side and the tag address register 80 When the address indicated by the content of the data block matches the address indicated by the contents of , and the flag V indicates the validity of the data block, a signal indicating a tag hit is sent to the outside from the gate 14b.The tag hit obtained in the above manner The signal is given to the cache control unit 16. This cache control unit 16 causes the cache data storage unit 10° to block tag storage unit 1.
2. Increment circuit 84 is controlled. FIG. 10 explains the zero clear processing at that time, and the hit of the tag is checked in the first processing cycle. Then, 8 bytes of zero clear data 101 are written to the address position of the cache data storage unit 1o indicated by the contents of the data address 82. Further, each time 8 bytes of zero clear data lot are written to the cache data storage unit io, the increment circuit 84 increments the contents of the data address register 82. The zero clear data 101 is sequentially written to the cache data storage unit 10 by 8 bytes while the address is incremented. The zero data writing is performed a total of 8 times until the corresponding data block is filled with 0. [Problems to be Solved by the Invention] However, in the past, zero clear processing is repeated in units of a predetermined data width until the target data block is completely filled with zero data. It becomes difficult to further shorten the time required for zero-clearing. The present invention has been made in view of the above-mentioned conventional circumstances, and
The purpose is to provide a device that allows data blocks in a cache to be cleared to zero at high speed. [Means for Solving the Problems] In order to achieve the above object, the device according to the present invention has the following features:
It is configured as shown in the figure. A plurality of data blocks are stored in the cache data storage means 10 shown in the figure, and these blocks are cleared to zero in units of a predetermined data width. Further, the block tag storage means 12 stores a tag for each data block of the cache data storage means 10.The tags include a first flag indicating whether the data block is valid or invalid, and a first flag indicating whether the data block is cleared to zero. A second flag indicating the data block and an address indicating the data block are included. Then, the tag hit signal output means 14 outputs a tag hit signal when it is confirmed that the first flag of the tag containing the address indicating the data block to be cleared to zero is valid. The tag hit signal is applied to the zero clear flag control signal 16. The second flag of the tag containing the address indicating the data block to be zero cleared is set to a state indicating zero clear of the data block. When the tag hit signal is output, the zero clear flag is controlled. The change is controlled by means 16. [Operation] In the present invention, when a tag hit is confirmed when a data block stored in the cache data storage means 10 is zero-cleared, the second flag of the corresponding tag is simply changed to a state indicating zero-clearing of the corresponding block. be done. Therefore, the corresponding block is not actually cleared to zero and is left as is. [Embodiment] Hereinafter, a preferred embodiment of the apparatus according to the present invention will be described based on the drawings. FIG. 2 shows the configuration of the embodiment, and each block tag stored in the block tag 12 has a cache block zero clear flag C shown in FIG. 3 added thereto. Further, gates 20.22 are provided on the write side and the successive output side of the cache data storage section 1o, respectively.The value of the cache block zero clear flag C included in the block tag read from the block tag storage section 12 is
2 inverting inputs, respectively. Here, when the above-mentioned microinstruction that clears one data block to zero is issued, the first address of that block is stored in the tag address register 80 as before.
．． It is set in the data address register 82. Then, when the tag hit of the target block is confirmed by the tag hit signal output unit 14 in the first processing cycle as shown in FIG. Hecache control unit 16
It can be rewritten by This flag value; 1 indicates that the block has been cleared to zero, and in this embodiment, by only rewriting the flag value, the zero clearing process is completed in one cycle as shown in FIG. 4. However, since the target block is not actually cleared to zero, when reading that block, it is necessary to output all data in the block in the form of zero-cleared data. FIG. 6 explains the operation when blocks occur one after another. In the case where the data of the block that has been temporarily cleared to zero as described above is called, and when a tag hit is confirmed, the data is read from the cache data storage unit 10. The cleared data is inhibited to 101 by the gate 22 by the cache block zero clear flag C. Therefore, the data is output in a zero cleared form. Next, a move-in operation is performed in the same manner as in the case of a tag mistake. At this time, the cache block zero clear flag C causes the data ζ suppressed by IQI at the gate 20 to be written to the corresponding block in the cache data storage unit 10 as if it were moved in from the main memory. After that, the cache block zero clear flag C is set to Cleared to 101. Therefore, there is no need to read the move-in data from the main memory, thereby reducing the load on the main memory. Incidentally, the increment of the cache address is 26 to 2.
Do this only for the 3 bits of 8. Next to tag 111" is "O".
OO”, the target block is cleared to zero (1 to 25 bits remain unchanged). Also, in the multiprocessor system shown in Figure 6, the cache block is transferred from one CPU side to the other CPU side. When reading is performed, if a tag hit is confirmed at the address of the read request as shown in FIG. The data is not read from the main memory, but from the cache data storage unit 1o that is the read request destination.During the move-out operation at that time, successive data in the cache data storage unit 10 is suppressed to 202 by the gate 22.
One block of zero data is sent to the data bus. Then, in the CPU to which the read request is made, 10 inches of zero data is moved into the cache data storage section 10 in the same manner as in the case of FIG. In this way, even in a multiprocessor system, other C
PU cache blocks can be accessed at high speed. As explained above, according to this embodiment, by simply setting a predetermined flag C included in the tag of a target block, the zero-clearing process for that block is completed, and a wide cache area can be zero-cleared extremely quickly. becomes possible.

【Effect of the invention】

As explained above, according to the present invention, the cache block corresponding to the hit tag is virtually cleared to zero just by changing the state of the ward flag, so there is no need to actually fill the block with zero data.
It becomes possible to perform zero clear processing on the cache area at extremely high speed.

[Brief explanation of drawings]

Figure 1 is an explanation of the principle of the invention. Figure 2 is an explanation of the overall configuration of the embodiment. 1 Figure 8 is an explanation of the tag configuration of the embodiment. Operation Explanation A Fig. 6 is an explanatory diagram of the configuration of a multiprocessor system. Fig. 7 is an explanation of the operation when blocks are successively executed by other CPUs. Fig. 8 is an explanation of the configuration of the conventional example. 1. Fig. 9 is an explanation of the tag configuration of the conventional example. FIG. 10 is a sixth explanation of the conventional zero clearing process. 10...Conflict cache data storage section 12...Block tag storage section 14...-Tag hit signal output section 14a, 14b...Gate 16...Cache control section 20.22Φ...Gate 80...Tag address Register 82...Data address register 84...An explanatory diagram of the tag configuration of the increment circuit embodiment. Figure 3. An explanatory diagram of the zero clearing process of the embodiment. Figure 4. An explanatory diagram of the tag configuration of the conventional example. Go to Figure 9. 1 toy

Claims (2)

[Claims] (1) Cache data storage means (10) for storing a plurality of data blocks with a predetermined data width as a unit; a first flag indicating whether the data block is valid or invalid; and a first flag indicating whether the data block has been cleared to zero. Tag storage means (1
2); and tag hit signal output means (14) for outputting a tag hit signal when it is confirmed that the data block is valid based on the first flag of the tag containing the address indicating the data block to be cleared to zero. , a zero-clear flag control means (16) for changing a second flag of the tag containing an address indicating a data block to be zero-cleared to a state indicating zero-clearing of the data block when a tag hit signal is output; A cache device featuring: (2) When a read request is made to a data block where the first flag is valid and the second flag is zero-cleared,
2. The cache device according to claim 1, further comprising read data zero control means (13) for setting the value of data read from the data block to zero.