JPS5822834B2 - Buffer invalid control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a buffer invalid control method, particularly in a system equipped with one or more processor devices that utilize a buffer memory, when the contents of the main memory are rewritten, the buffer - When performing buffer invalidation processing to invalidate the contents of memory, when the same invalid address is repeatedly transferred multiple times, only one of them will be accepted, making the buffer invalidation processing more efficient. This paper relates to a buffer invalid control method.

In a data processing system that uses a so-called buffer memory, the contents of the main memory are transferred to the buffer memory in units of, for example, 1 block (32 bytes), and the processor device accesses the buffer memory and transfers the contents to the buffer memory. process? Progress (.

In this case, for example, when a processor device under a multiprocessor system rewrites the contents of the main memory,
Since the contents of the rewritten address may have been transferred to the buffer memory, the rewritten address is transferred to the buffer memory as an invalid address.

Then, on the buffer memory side, processing is performed to invalidate the contents of the buffer memory using the transferred invalid address.

In this case, since the memory may be busy in the processor device to which the invalid address is sent, conventionally the sent invalid address is temporarily held in an invalid address register. things are done.

Needless to say, when performing such retention, care is taken to ensure that logical contradictions do not occur during the period when the invalid processing is not completed.

That is, for example, if a block load is performed from the main memory within an unfinished period, the invalidation process is correctly completed.

Note that in this specification, the term invalid address is used to mean an address that is invalid.

Performing the buffer invalidity control as described above involves the following problems.

That is, the process of rewriting the contents of the main storage device is, for example, 1.
This is done in bytes to 8 bytes, but on the other hand, it is transferred to the buffer memory in blocks (32 bytes), and the buffer invalidation process described above is carried out in units of one block that includes the rewritten address. .

For this reason, when a process such as sequentially rewriting the contents belonging to the same block unit is performed on the main memory side, even though the desired buffer invalidation process is terminated by the first invalid address given. ,
The same invalid address will be given one after another.

That is, on the buffer memory side, invalidation processing must be performed repeatedly and unnecessarily.

The purpose of the present invention is to solve the above problem, and when an invalid address is transferred that has the same content as the invalid address that was previously given and set in the invalid address register, The purpose is to ignore unnecessary invalid processing.

Therefore, the buffer invalid control method of the present invention includes a main memory device and one or more processor devices, and transfers a predetermined unit of data on the main memory device to the buffer memory. In a data processing system in which the processor device advances processing while accessing the buffer memory, an invalid address is transferred that invalidates the contents of the buffer memory when the contents of the main memory are rewritten. In addition to providing an address register, a comparison circuit is provided to compare the contents of the invalid address register with the transferred invalid address, and only when the comparison circuit generates a mismatch output, the transferred invalid address is・The above address is invalid.
The feature is that it is set in the address register.

This will be explained below with reference to the drawings.

The figure shows the configuration of an embodiment of the present invention.

In the figure, numeral 1 is a main storage device, 2A and 2B are storage control devices that mediate access requests from each processor device, 3A, 3B, 4A, and 4B are processor devices, respectively, and 5A and 5B are each a storage control device. In this embodiment, the buffer memory is provided in the storage control unit SCU, and 6A and 6B are tag sections of the buffer memory, respectively, in which addresses of data stored in the data section, which will be described later, are stored. 7A and 7B are the data portions of the buffer memory, in which data is transferred from the main memory in units of bytes as described above, and 8A and 8B are invalid address registers, respectively. The one where the invalid address to be transferred is set,
F is a flag bit, 9A and 9B are comparison circuits produced by the present invention, and 10A and 10B are AND circuits, respectively.

For example, when the processor device 3A proceeds with processing,
Processing is performed while accessing the buffer memory 5A or 5B.

The data needed during this time is stored in buffer memory 5A or 5B.
If the block does not exist on main storage 1,
When the load is interrupted, the contents on the main memory device 1 are transferred to the data section IA of the buffer memory 5A or 5B in block units.
or 7B, and address information corresponding to the transferred content is stored in the tag section 6A or 6B.

While the processing is proceeding as described above, for example, if the processor unit 3B rewrites the contents on the main memory 1, the above-mentioned invalid address (INV/ADR8) is given to the buffer memories 1J5A and 5B. It will be done.

That is, if the rewritten address exists on the tag section 6A or 6B of the buffer memory, an invalid bit is set on the tag section 6A or 6B, invalidating the content on the data section 7A or 7B. The processing to do so will be performed.

In this case, as described above (an invalid address is an address that specifies a block unit).

Given for each rewrite.

Therefore, when addresses belonging to the same block unit are sequentially rewritten on the main memory device, the same invalid address will be given one after another.

In other words, on the buffer memory side, even though it is possible to perform the necessary buffer invalidation processing due to the invalid address that was first transferred, the same buffer invalidation processing has to be performed unnecessarily. .

Therefore, in the case of the present invention, invalid addresses (I
When the NV-ADR 8) is transferred, the address is compared with, for example, the contents of the first stage of invalid address registers 8A and 8B by comparison circuits 9A and 9B.

If there is a mismatch, the transferred invalid address is set in the first stage via AND circuits 10A and 10B.

Then, the flag bit is set to logic "1".

If they match, the transferred invalid address is ignored.

Buffer invalid processing is performed in buffer memory 5A or 5B based on the contents of the final stage of invalid address register 8A or 8B.

Upon completion of the processing, the contents of invalid address register 8A or 8B are shifted downward one stage at a time.

However, the invalid address set in the first stage remains without being deleted.

During this shift, the flag pin (F) is also shifted together, and the flag pin (F) in the first stage is set to logic "0".

If the above shift operation is performed before a new invalid address has been transferred, the invalid address stored in the first stage without being deleted is shifted to the second stage, but Flag bit F is shifted to a logic '0';

Needless to say, even if an invalid address with flag bit F at logic "0" is output from the final stage of invalid address register 8A or 8B, no buffer invalidation processing is performed.

As mentioned above, invalid addresses are not erased (or saved) in the first stage of register 8A or 8B, so as long as the same impad address is continuously transferred, they will be ignored one after another.

In addition, invalid address register 8A or 8
If each crotch is full of invalid addresses in any one of B, this is detected by the flag bit, and the process of rewriting the contents of the main memory 1 is prohibited.

This prevents the contents of the main storage device 1 from becoming inconsistent with the contents on the buffer memory.

As described above, according to the present invention, the same invalid address is not repeatedly given and unnecessary buffer invalidation processing is not executed (processing efficiency can be improved).

In addition, in the above description, the buffer memories 5A, 5B
Although the case where the computer is installed on a storage control device is shown, it goes without saying that the same effect can be achieved even if the computer is installed on a processor device.

[Brief explanation of the drawing]

The figure shows the configuration of an embodiment of the present invention. In the figure, 1 represents a main storage device, 2 a storage control device, 3 and 4 processor devices, 5 a buffer memory, 8 an invalid address register, F a flag bit, and 9 a comparison circuit.

Claims (1)

[Scope of Claims] 1. A main storage device and one or more processor devices, wherein a predetermined unit of data on the main storage device is transferred onto a buffer memory, and the processor device In a data processing system that advances processing while accessing a buffer memory, an invalid address register is provided to which an invalid address that invalidates the contents of the buffer memory is transferred when the contents of the main memory are rewritten. and a comparison circuit that compares the contents of the invalid address register with the transferred invalid address,
A buffer invalid control system characterized in that the transferred invalid address is set in the invalid address register only when the comparator circuit issues a non-coincidence output. 2 The above invalid address register is composed of multiple stages that shift the set invalid address upon completion of processing in which the contents of the buffer memory are invalidated according to the set invalid address. 2. A buffer invalid control system according to claim 1, wherein said comparison circuit is provided corresponding to one predetermined stage of said invalid address register. 3. A flag bit is created corresponding to each stage of the invalid address register, and when the flag bits of all stages are set, rewriting of the contents of the main memory is prohibited. A buffer invalid control method according to claim 2. 4. The invalid address set in the stage to which the comparator circuit is associated in the invalid address register is configured to be retained without being erased even after being shifted to the next stage. A buffer invalid control method according to claim 2, characterized in that: