JPS63157255A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the shift value of a reading main memory by shifting addresses and their contents written successively into a writing main memory to the reading main memory without shifting all contents of the writing main memory to the reading main memory when the stored generations are updated. CONSTITUTION:The processors 200 and 201 complete the processing to be executed in the present stored generation and delivers an instruction for request of updating of stored generations. Then the processors 200 and 201 output the generation updating request signals 300 and 301 after execution of instructions. While an AND circuit 303 outputs '1' to start a control circuit 304. Then a generation updating command signal 306 is sent to a main memory. The contents of the processing result written into a writing main memory 101 are shifted to the corresponding address of a reading main memory 100 by the signal 306. When this shift is through, the circuit 304 sends a generation updating end signal 302 to both processors 200 and 201. Thus the updating of generations is restarted.

Description

[Detailed description of the invention] [Industrial application field] This Sanskrit is r311i for information processing equipment.

[Conventional technique]

FIG. 3 is a conceptual diagram of a conventional information processing device (phono-Neumann type meter). This information center Ili! The device consists of a processor 401 and a main memory 400. There are a number of storage locations in main memory 400, and data A read from a selected one a is sent to processor 401. Next, data B read from another storage location vb in main memory 400 is also sent to processor 401. The result C processed by the processor 401 is stored in the main memory 4
00 is written to another memory location C.

Note Q1 What should be done here is that in conventional computers, the data C written in the memory location IC is transferred to the processor 4.
The problem lies in the fact that the program is based on the premise that 01 can be immediately read and used. That is, access to the main memory 400 must basically be performed in the order of f, which is incremented by 1 in the program. Therefore, for the same set of data? In order to simultaneously perform parallel processing with l number of processors, complicated restrictive conditions are required.

In order to solve the above problems, an information processing device with a new architecture that allows a large number of processors to process a series of data in parallel was proposed, for example, in
011 in No. 7664. This information center! I!
The main memory of the device consists of a read main memory and a fortune-telling main memory that are accessed by multiple processors, and after the processing of the processors is completed, all the contents of one write memory are transferred to the read main memory. It was supposed to be moved.

However, transferring all the contents of the feeding main memory to the reading main memory after the processing of the processor is completed causes the transfer 1d to the reading main memory to become enormous.

[Problem that the invention attempts to solve]

The above-mentioned conventional information processing device is provided with a main memory for reading and a main memory for filling, and a storage generation management 1734riS for updating the storage generation, and has a main memory for reading from a plurality of processors. After the data in the memory is accessed and the process is completed, the contents of all memory locations in the main memory for reading are moved to the corresponding memory locations in the main memory for reading by an instruction that requests an update of the memory generation. Because simultaneous parallel processing was being performed, trX11! When updating a memory, the contents of all memory locations are moved from the main memory for reading to the main memory for reading, regardless of whether or not there is access to the memory location for writing from the boot tree. This has the disadvantage that the amount of data transferred to the main memory for reading becomes enormous and the performance of simultaneous parallel processing deteriorates.

[Means for solving problems]

The information processing device of the present invention includes at least one processor, a read storage section that stores a plurality of storage locations, and a write storage section that sequentially stores write storage locations and contents from the processor, It is detected that the main memory previously accessed by the processor and the data in the read memory by all the processors have been completed, and the contents of the memory location in the write memory are transferred to the read memory. It has a control circuit for moving the memory to the corresponding memory location of the section.

[Effect]

FIG. 1 is a conceptual diagram of an information processing apparatus according to the present invention.

The main memory consists of a read main memory 100 and a read main memory 101. Main memory 100 for reading
The storage location 1 and the storage location 1 stored in main memory 101 for writing are accessed using the same address. Processors 200 and 201 are connected to the reading memory 100 and the writing main memory 101. each processor 20
0.201 reads data from the read main memory 100, processes it, and transfers the result of A to the write main memory 10.
1. Fill in the storage position of the processing result according to the order in the storage space L 101 that has no relationship with 1.1. each processor 20
0.201 uses the same address to specify any storage location.

The program for the information processing device 9a of the present invention reads out data from the main memory 100 for reading all data and stores it in the store.
It is designed to be written to 101, so broset 472
00.201 accesses the read main memory 100 in any order, the erased result is constant. however,
Processor 200 to the same location of the access soil 101
．． When 201 writes data into λ, the writing order has an influence. Normally, you can write a program to the same address more than once to avoid damaging data.

When the master processors 200 and 201 finish processing the data in the current reading memory 100, the memory generation is updated.The memory generation is updated by one process 111 in this memory. Specifically, the storage location and contents of the processing results stored in the reading media 101 are to be moved to the corresponding storage locations in the reading media 100. After this storage generation has been updated, each processor 200, 201 reads the processing result of the previous storage generation and uses it as data.0111 The next stage of processing begins. It means that it may be done.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows the information processing T! of the present invention shown in FIG. I! It is a block diagram of an embodiment of the equipment.

This embodiment consists of a processor 200, 201, a main memory, and a storage generation management mechanism 305. The main memory consists of a read-out host memory 100 and a write-in main memory 101. Main memory for reading 100 and main memory for writing 101 are accessed by processors 200 and 201 using the same address. Memory generation management mechanism 30
5 is the logic I! of the generation update request signal 300.301 output from the processor 200.20.1. lF? AND circuit 22!303 that takes 4, and a control circuit 304 that sends a generation update command signal 306 to the main memory 100 by the output of the AND circuit 303, and outputs a generation update completion signal 302 to the processors 200 and 201 when the memory generation update is completed. It is.

When each of the processors 200 and 201 completes all processing to be executed in the current memory generation, it issues an instruction requesting update of the memory generation. When this instruction is executed, the processors 200 and 201 send generation update request signals 300 and 30.
Outputs 1 and enters the period state. all processors 20
When 0.201 executes an instruction to request an update of the memory generation, the AND circuit 303 outputs an output signal of ``1'', and the control circuit 304 operates to issue a generation update command signal 306.
is sent to main memory. As a result, in the main memory, the contents of the storage location of the processing result written in the main memory for writing 102 are moved to the corresponding storage location of the main memory for reading 101. When the above-mentioned storage generation update is completed in the main memory, the control circuit 30'4 sends a generation update completion signal 1302 to the processors 200 and 201. When the processors 200 and 201 in the current state receive the generation update completion signal 302, they start processing again and can read out the processing results of the previous storage generation and use them as data.

That is, it means that the next stage of processing may be started.

Note that the storage generation management mechanism 305 may be located in either the main memory or the processors 200, 201, or may be distributed among a plurality of them.

〔Effect of the invention〕

As explained above, in the present invention, when it is detected that the main memory for reading is accessed by a plurality of processors in simultaneous parallel processing, and the main memory for writing is accessed by a plurality of processors, the main memory for writing is A control circuit is provided so that the contents of the memory are not moved to the corresponding storage location in the main memory for reading, and when updating the memory generation, the contents of the main memory for writing are not transferred entirely to the main memory for reading, but are stored in the main memory for writing in order. Written memory position II! By moving only (address) and its contents, the amount of transfer to main memory for reading is reduced. This has the effect of increasing the performance of processing execution.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of an information processing device of the present invention, FIG. 2 is a block diagram of an embodiment of the information processing device of the present invention, and FIG. 3 is a conceptual diagram of a conventional information processing device. 100...Main memory for reading, 101...Main memory for writing, 200.201...Bu [1t? Tuna, 300.301
...Generation update request signal, 302... Generation update completion signal, 303... AND circuit, 304... Control circuit, 305... Memory m generation management mechanism, 306... Generation update command signal. Figure 1 Figure 3

Claims (1)

[Scope of Claims] A processor comprising: at least one processor; a read memory having a plurality of memory locations; and a write memory in which write memory locations and contents from the processor are sequentially stored; Detecting that the accessed main memory and all the processors have finished processing the data in the read memory, and transfer the contents of the memory location in the write memory to the corresponding one in the read memory. An information processing device having a control circuit for moving the data to a storage location.