JPS63157256A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the shift value of the contents of a writing memory part to a reading memory part and to improve the working performance of an information processor, by shifting the contents of the writing memory part after detecting that all processors finished their processes to the data of the reading memory part. CONSTITUTION:The processors 200 and 201 complete all processes to be executed in the present stored generation and deliver the instructions for request of updating of generations. When both processors 200 and 201 carry out said instructions, an output signal of 1 is outputted from an AND circuit 303. A control circuit 304 works to send a generation updating command signal 306 to a main memory. In the main memory a write address main memory 102 outputs a generation updating address signal 103 and the contents of the memory positions of a writing main memory 101 corresponding to the memory positions (addresses) stored in the memory 102 in a prescribed order are shifted to the corresponding memory positions of a reading main memory 100.

Description

[Detailed description of the invention] [Industrial application field] The present invention is information processing I! 1! Regarding equipment.

[Conventional technology]

Figure 3 shows a conventional information processing device (phono-neumann
It is a conceptual diagram of the i-machine). This information processing device consists of a processor 401 and a main memory 400. Main memory 4
There are a large number of storage locations in 00, and data 8 read from a selected one a is sent to the processor 401. Next, the data 8 read from the storage unit Hb in the memory 400 is also sent to the memory 401. The bundle C processed by the processor 401 is written to another memory location HC+: in the main memory 400.

What should be noted here is that in conventional 5L moderators, the processor 401 can immediately read and use the data C stored in the memory section @cc. It is at the point where it is 19 degrees. That is, access to the main memory 400 basically has to be performed by procedure C written in the program. Therefore, do multiple processors have the same number for the same set of data? 1 (This caused the need for troublesome restrictive conditions in order to make a difference.

In order to solve the above problems, an information processing device with a new architecture that allows a large number of processors to process a series of data in parallel is proposed, for example.
7 (disclosed in No. 364). This information processing device is
It consists of two main memories, a read main memory and a write main memory, which are accessed by multiple processors on the main memory.
After the processor finishes processing, all the contents of the write main memory are transferred to the read main memory. However, transferring the entire contents of the write main memory to the read main memory after processing ppmY by the processor causes an enormous amount of data to be transferred to the read main memory.

(Problems to be Solved by the Invention) The conventional information processing device described above has two main memories, a reading main memory and a writing main memory, and a storage generation management mechanism for updating the storage generation. , data in the read main memory is accessed by multiple processors to execute processing, and after the processing is completed, the contents of all storage locations in the write main memory are updated to correspond to the read J memory by an instruction that requests an update of the memory generation. When the memory generation is updated, the contents of all memory locations are transferred to the memory area l for writing, regardless of whether or not there is access from the processor to the memory location in the main memory for writing. There is a drawback that the amount of data transferred from the memory to the main memory for reading becomes enormous and the performance of simultaneous parallel processing deteriorates.

[Means for solving problems]

The information processing device of the present invention includes: at least one processor; a read storage section having a plurality of storage locations; a write storage section having a plurality of t11 positions corresponding to the plurality of storage locations of the storage section; a write address storage section in which only memory locations accessed by the processor are sequentially stored in the write storage section, and a main memory accessed by the processor; Detecting that the processing for the data in the read storage unit is completed, and transfer the contents of the storage location in the write storage unit according to the write address storage unit to the corresponding storage location in the read storage unit. It has a control circuit for transferring the data.

[Effect]

FIG. 1 is a conceptual diagram of an information processing apparatus according to the present invention.

The main memory consists of a main memory 100 for reading, a main memory 101 for reading, and a main memory 102 for writing addresses. For reading, write ↑MeDsu100.

Embedded main memory 101 has similar storage locations, and corresponding storage locations in each memory 100.101 are accessed using the same address. Main memory 1 for circular address
The same applies to the storage location stored in 02. The main memory 100 for reading, the main memory 101 for reading, and the main memory 102 for reading addresses include processors 200 and 20.
1 is connected. Each of the processors 200 and 201 reads data from the reading memory L 100 and processes it, and writes the result to the main memory 101 for reading and writing, and at the same time stores only the storage location (address) in the main memory 102 for reading addresses. Insert in order. Processor 200.201
Both use the same address to specify any storage location.

Since all programs of the information processing apparatus of the present invention are designed to read data from the main memory for reading 100 and write it to the main memory for stacking 101, the processor 200
．． 201 accesses the read main memory 100 in any order, 1! The results obtained are constant. However, the processor 200,
When 201 ages the arc, the order of its entry and exit is j
) J+, IT b. Normally, data is programmed in one program to prevent data from being written to the same address more than once.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the information processing apparatus of the present invention shown in FIG.

This embodiment consists of a program tree 200, 201, a main memory, and a storage generation tube 1! ! It consists of aircraft 1305. The main memory includes a read main memory 100 and a write main memory 10.
1 and a main memory 102 for write addresses.

The read main memory 100 and the write memory 101 have similar storage locations, and corresponding storage locations in each memory 100.101 are accessed using the same address.

The same applies to the storage locations stored in the write address main memory 102. Memory generation'r! ! Science and Engineering 305
is an AND circuit 303 that takes the AND of the generation update request signals 300 and 301 output from the processors 200 and 201.
The generation update command signal 3 is generated by the output of the AND circuit 303.
A control circuit 304 sends a generation update completion signal 302 and a generation update completion signal 302 to the processors 200 and 201 when the storage generation update is completed.

When each of the processors 200 and 201 completes all processing to be executed in the current memory generation, it issues an instruction requesting update of the memory generation. When this instruction is executed, the processor 200.201 sends a generation update request signal 300.30.
Roll a 1 and enter the period state. all processors 200
．． When 201 executes an instruction requesting update of the memory generation, the AND circuit 303 outputs an output signal of ``1''', and the control circuit 304 operates to send the generation update command signal 306 to the main memory. , in the main memory, the write address main memory 102 receives the generation update address signal 1.
03 is output, and the contents of the memory location of the write main memory 101 corresponding to the memory location (address) are stored in the write address main memory 102 in a determined order. The data is moved to the corresponding storage location.At this time, the storage contents of the write main memory 101 do not change.

When the above-mentioned storage generation update is completed in the main mode, the core control circuit 304 sends the generation update completion signal 302 to the processor 20.
Send to 0.201. Processor 200 that was in the period state
．． When the generation completion signal 302 is received, the processor 201 starts processing again, and each processor 200 and 201 can read the processing result of the previous storage generation and use it as data.

Note that the memory t[j management mechanism 305 may be located in either the main memory or the prohira υ200.201,
Or it may be distributed among a plurality of them.

〔Effect of the invention〕

As explained above, the present invention provides a main memory for reading, a main memory for writing, a main memory for outputting addresses, and a main memory for reading that are accessed from a plurality of prohiras υ in simultaneous parallel processing, and a processor having finished processing the main memory for reading. When this is detected, the memory location (
By providing a control circuit that moves the contents of the storage location in the main memory for readout to the main memory for readout according to the address) °, all the contents of the main memory for write access are transferred to the main memory for readout access when updating the memory generation. This makes it possible to transfer only the contents of the storage location stored in the main memory for write addresses, thereby reducing the amount of transfer to the main memory for reading and improving the performance of processing execution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention, and FIGS. 2 and 3 are conceptual diagrams of conventional examples. 100... Main memory for reading, 101... Writing m1 memory, 102... 19 address memory, 103...
- Generation update address signal, 200.201... Processor, 300.301... Generation update request signal, 302...
Generation update completion signal, 303...AND circuit, 304...Control circuit, 305...Storage generation management m structure, 306...Generation update command signal. Agent Patent Attorney Uchimai, Pa\-
Le'

Claims (1)

[Scope of Claims] At least one processor; a read memory having a plurality of memory locations; a write memory having a plurality of memory locations corresponding to the memory locations of the memory; a write address storage section in which only storage locations accessed by the processor are sequentially stored; a main storage device that is accessed by the processor; and a storage section for reading by all the processors. a control circuit that detects that processing for the data has been completed and moves the contents of the storage location in the write storage section corresponding to the write address storage section only to the corresponding storage location of the elicitation storage section. An information processing device with