JPS5693165A - Data process system - Google Patents

Abstract

PURPOSE: To reduce the sending frequency of the store address in a simple and effective way, by storing the store address having an invalidated data of a buffer memory in the address buffer memory and then inhibiting the sending of the new store address which coincides with the contents of the store address buffer memory.

CONSTITUTION: When a coincidence is obtained between the new store address given from the control circuit part 12 which performs the busy check, decision of priority and others for a memory control device and the store address wherein the data of the buffer memory stored in the address buffer memory 21 etc. are invalidated, the gate circuit 27 etc. are closed via the comparators 23 etc. to inhibit the setting of the new store address to the register 13-2. While in case no coincidence is secured for the new store address, not only the circuit 27 but the gate circuit 25 are opened. Thus the address set to the register 13-2 makes the buffer memory of the CPU1 and others invalid. At the same time, the contents of the memory 21 is renewed. Accordingly, the sending frequency of the store address can be reduced effectively without affecting other factors, thus increasing the processing speed.

COPYRIGHT: (C)1981,JPO&Japio