JPS56156980A - Data processor - Google Patents

Data processor

Info

Publication number
JPS56156980A
JPS56156980A JP5908780A JP5908780A JPS56156980A JP S56156980 A JPS56156980 A JP S56156980A JP 5908780 A JP5908780 A JP 5908780A JP 5908780 A JP5908780 A JP 5908780A JP S56156980 A JPS56156980 A JP S56156980A
Authority
JP
Japan
Prior art keywords
memory
contents
cash
coincide
cash memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5908780A
Other languages
Japanese (ja)
Other versions
JPS60701B2 (en
Inventor
Hiroshi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55059087A priority Critical patent/JPS60701B2/en
Publication of JPS56156980A publication Critical patent/JPS56156980A/en
Publication of JPS60701B2 publication Critical patent/JPS60701B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To allow the contents of the cash memory and main memory of a multiprocessor system to coincide at all times by detecting the overflow of an address stack register thereby invalidating the entire contents of the cash memory. CONSTITUTION:The contents of the main memory 23 and cash memory 1 of the multiprocessor system are so processed as to coincide at all times unless the memory 23 is rewritten by other device based on the readout request via an arithmetic part 4 when they do not coincide. When a stack register 6 gets full with the transferred addresses during this processing and overflows, this is detected 7, and a cash memory unsable signal is transmitted to a cash memory control part 5 through a cash memory invalidation control part 8, thereby invalidating the entire part of the memory 1. This obviates the occurrence of dissidence of the contents of the memories 1, 2 owing to the annhilation of the unprocessed addresses.
JP55059087A 1980-05-01 1980-05-01 data processing equipment Expired JPS60701B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55059087A JPS60701B2 (en) 1980-05-01 1980-05-01 data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55059087A JPS60701B2 (en) 1980-05-01 1980-05-01 data processing equipment

Publications (2)

Publication Number Publication Date
JPS56156980A true JPS56156980A (en) 1981-12-03
JPS60701B2 JPS60701B2 (en) 1985-01-09

Family

ID=13103202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55059087A Expired JPS60701B2 (en) 1980-05-01 1980-05-01 data processing equipment

Country Status (1)

Country Link
JP (1) JPS60701B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167891A (en) * 1983-03-14 1984-09-21 Nec Corp Buffer storage device
JPS6478342A (en) * 1987-09-19 1989-03-23 Pfu Ltd Invalidation processing system for cache memory
JPH0272453A (en) * 1988-06-27 1990-03-12 Digital Equip Corp <Dec> Multiprocessor computer system having shared memory and private cash memory
JPH0561771A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Partial purge processing system for tlb

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6181602A (en) * 1984-09-28 1986-04-25 松下電器産業株式会社 Varister

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59167891A (en) * 1983-03-14 1984-09-21 Nec Corp Buffer storage device
JPS6478342A (en) * 1987-09-19 1989-03-23 Pfu Ltd Invalidation processing system for cache memory
JPH0272453A (en) * 1988-06-27 1990-03-12 Digital Equip Corp <Dec> Multiprocessor computer system having shared memory and private cash memory
JPH0561771A (en) * 1991-09-04 1993-03-12 Fujitsu Ltd Partial purge processing system for tlb

Also Published As

Publication number Publication date
JPS60701B2 (en) 1985-01-09

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