JPH0561771A - Partial purge processing system for tlb - Google Patents

Abstract

PURPOSE:To efficiently use a TLB while avoiding full purge by suppressing the read of a new instruction when the number of addresses as the objects of partial purge is turned to the maximum number to be held. CONSTITUTION:This system is equipped with a register 1 to hold a signal showing the validity of the address as the object of the partial purge, partial purge control part 2 to issue a partial purge request SR-REQ, and judgement part 5 to issue an instruction read suppressing request INH-IU-REQ and when the signal showing the validity of the address as the object of the partial purge is set to the register 1, the partial purge control part 2 executes the partial purge by issuing the partial purge request SR-REQ. When the judgement part 5 judges that the signal showing the validity for the prescribed number (the maximum number) of addresses is set to the register 1, the instruction read suppressing request INH-IU-REQ is issued so as to suppress the read of the new instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a partial purging system for partial purging of TLB.

[0002]

2. Description of the Related Art When an information processing device has a TLB, the SS
K (Set Storage Key) and IPTE (Invalidate Page Tagl)
For commands such as e Entry), it is necessary to partially purge the TLB. When multiple CPUs share main memory, partial purge must be performed by all CPUs, so SSK, I
The CPU fetching the PTE instruction sends the invalidation request BI-REQ to all the CPUs via the MCU, and each CPU receiving the invalidation request invalidates the corresponding entry.

Here, while the SSK and IPTE commands are commands designated by real addresses, TLB is indexed by logical address, and therefore all TLB entries are searched in order to perform partial purging of TLB. There is a need. For this reason, conventionally, for example, OI-PPAR0 and OI have been used as registers for holding addresses to be partially purged.
The two units of -PPAR1 are held in the S unit, the partial purge request SR-REQ is issued, the TLB is searched, and the corresponding entry is erased (partial purge). Then, when there are two or more addresses that are the targets of the partial purge, the all purge request PT-REQ is issued to invalidate the entries of all TLBs (control flow of FIG. 4). reference).

FIG. 4 is an explanatory view of the prior art. Register OI-PPAR0-VLD into OI-P
A signal indicating that the address held in PAR0 is valid is held, and a partial purge request SR-REQ of TLB is issued.

Is followed by register OI-PPAR1
A signal indicating that the address of OI-PPAR1 is valid is held in -VLD, and a partial purge request SR-REQ of TLB is issued.

Then, at the time of the third partial purge, the register CHG-TO-PTLB holds a signal indicating that the third and subsequent partial purge requests have come, and the TLB total purge request PT. -Issue REQ.

In response to the above issuance of all purge requests PT-REQ, all TLB entries are invalidated. As described above, conventionally, up to two addresses to be partially purged can be held, but when the number becomes three or more, the entire purge is performed.

[0008]

Therefore, when two or more addresses to be partially purged are held and a third invalidation request comes, an all purge request PT-REQ is issued and all TLB entries are issued. However, there is a problem that the logical address cannot be converted into the real address at high speed until the pair of the logical address and the real address is registered again.

The present invention suppresses the reading of a new instruction when the number of addresses to be partially purged of the TLB reaches the maximum number that can be held, and avoids the entire purge to avoid the TLB.
Is intended to be used efficiently.

[0010]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, a register 1 is a register that holds a predetermined number of signals indicating that an address targeted for partial purge is valid, corresponding to a TLB invalidation request BI-REQ.

The partial purge controller 2 issues a partial purge request SR-REQ to carry out a partial purge of TLB when a signal indicating that the address to be the partial purge target is valid is held in the register 1. It is a thing.

The judgment unit 5 judges whether or not the number of signals indicating that the address to be partially purged which can be held in the register 1 is valid has reached a predetermined value (for example, maximum value), and the value is set to the predetermined value. INH-
The IU-REQ is issued and reception of reading of a new instruction is suppressed.

[0013]

According to the present invention, as shown in FIG. 1, when a signal indicating that the target address of the partial purge is valid is set in the register 1 in response to the TLB invalidation request BI-REQ. The partial purge control unit 2 requests the partial purge SR-
When the REQ is issued to perform the partial purging of the TLB, and the determination unit 5 determines that the signal indicating that the target address of the partial purge having the predetermined value (for example, the maximum number) is valid is set in the register 1. , Instruction read suppression request INH
-IU-REQ is issued to prevent reading of a new instruction.

Therefore, by suppressing the reading of a new instruction when the maximum number of addresses that can be held by the target of partial purging of TLB is reached, all purging is avoided and TLB is used efficiently. It is possible to perform address conversion at high speed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of one embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 1A shows a configuration diagram. In (a) of FIG. 1, the register 1 corresponds to the TLB invalidation request + BI-REQ, and through the pipeline registers OI-PBTR and OI-JBTR, the target address (real address) ) Are registers OI-PRAR0-VLD and OI-PPAR1-VLD which hold a predetermined number (two in this case) of signals indicating that they are valid.
The address is a pipeline register OI-PBA not shown.
It is held in registers OI-PPAR0 and OI-PPAR1 via R and OI-JBAR.

When the partial purge control unit 2 sets a signal indicating that the target address (real address) of the partial purge is valid in the registers OI-PRAR0-VLD and OI-PPAR1-VLD which are the register 1 Then, a partial purge request + SR-REQ for performing a partial purge of the TLB of this address is issued. In response to the issuance of this partial purge request + SR-REQ, the corresponding entry of the TLB in the S-UNIT of FIG. 2 is searched and found to invalidate it.

Register CHG-TO-PTLB which is register 3
Holds a signal in the registers OI-PRAR0-VLD and OI-PPAR1-VLD indicating that the two addresses subject to partial purge are valid, and confirms that more partial purge targets are valid. It is a register for setting information for performing the full purging of the TLB when the signal shown is notified.

The all purge control unit 4 requests all purge of the TLB + PT-RE when all the purge information is set in the register CHG-TO-PTLB which is the register 3.
Issuing Q. In response to the issuance of all purge request + PT-REQ, all entries of the TLB in S-UNIT in FIG. 2 are invalidated.

FIG. 1B shows an explanatory diagram for determining the instruction read inhibition request. In FIG. 1B, the determination unit 5 is the register 1 which is the register OI-PRAR0-VLD, OI-P.
It is determined whether or not a signal indicating that the target address of the partial purge is valid is held in two of PAR1-VLD, and YES
When it is found that the instruction read inhibition request + INH-IU-REQ is issued, the S-UNIT in FIG. 2 inhibits the acceptance of the reading of a new instruction from the I-UNIT. As a result, the reading of a new instruction is suppressed, and during this time, the partial purging of the corresponding entry of the TLB is performed for the address targeted for the partial purging, and the corresponding one of the registers OI-PRAR0-VLD and OI-PPAR1-VLD is deleted. clear. And instruction read suppression request + INH-IU-
Release REQ, S-UNIT accepts the reading of the instruction,
continue processing.

The judging section 5-1 includes a register 1 and a register 3
It is to determine whether or not to set a signal indicating that the address of the partial purge target is valid. Judgment unit 5
-2 judges whether the signal indicating that the target address (real address) of the partial purge is valid is set in register OI-PPAR0-VLD which is register 1, and when it is not set, By + SET-OI-PPAR0-VLD, a signal indicating that the target address of the partial purge is valid is set in the register OI-PPAR0-VLD.

Similarly, the determination unit 5-3 sets a signal indicating that the address of the partial purge target is valid in the register OI-PPAR0-VLD which is the register 1 (+ OI-PPAR0-VLD).
D), and the signal indicating that the target address of the partial purge is valid is not set in the register OI-PPAR1-VLD.
(-OI-PPAR1-VLD), and if YES, + SET-OI-P
PAR1-VLD sets a signal indicating that the target address of the partial purge is valid in the register OI-PPAR1-VLD.

Similarly, in the judging section 5-4, a signal indicating that the address of the partial purge target is valid is set in the register OI-PPAR0-VLD which is the register 1 (+ OI-PPAR0-VLD).
D) and a signal indicating that the target address of the partial purge is valid is set in the register OI-PPAR1-VLD (+ OI-PPA
(R1-VLD), and if YES, + SET-CHG-TO
-Register CHG-TO-PTLB with information on all purges via PTLB
To be set to.

FIG. 2 shows the overall configuration of the present invention. Figure 2
In the above, CPU0 and CPU1 are central processing units, and are S-UNIT (Storage UNIT) and I-UNIT (Instr
Auction UNIT) and E-UNIT (Execution UNIT). I-UNIT requests reading of instructions by sending IU-REQ to S-UNIT, and S-UNIT
Control execution of instructions received from the CHE (cache memory). S-UNIT is BI-REQ (invalidation request),
MI-REQ (move-in request, request to read data, command, etc. from MU (main memory) to CHE), TR-REQ (dynamic address translation request), SR-REQ (TLB to be partially purged)
Search request), PT-REQ (TLB purge request), IU-R
Execute EQ (request to read command from CHE to I-UNIT).

Here, while SSK and IPTE are instructions designated by real addresses, TLB is indexed by logical addresses. For this reason, it is necessary to partially purge the TLB and
, And the two registers 1 of OI-PPAR0-VLD and OI-PPAR1-VLD that hold the signal indicating that the address (real address) that is the target of partial purge is valid are S-UNIT Provided inside these registers, these registers OI-PPAR0
-VLD and OI-PPAR1-VLD are the above-mentioned decision unit 5 in FIG.
A signal indicating that the address (actual address of the partial purge target) transmitted through the pipeline by -1, 5-2, 5-3 is valid is set. After this setting, the PPTLB CONTROL which is the partial purge control unit 2 issues a partial purge request + SR-REQ to request the search of the entry of the TLB to be partially purged and invalidate it.

The registers OI-PPAR0-VLD, OI-PPAR1
-If a signal indicating that the real address for which a BI request (invalidation request) has been issued to two VLDs remains valid, and if the next partial purge request is transmitted to the pipeline, TL
It is necessary to completely purge B, and when this is detected by the determination unit 5-4 in (b) of FIG. 1, + SET-CHG-TO-PTLB
When it is set in the register CHG-TO-PTLB which is the register 3 by the PTLB controller, the PTLB CONTROL which is the all purge control unit 4 issues the all purge request + PT-REQ to request all the purges of the TLBs and all the TLBs. Invalidate the entry.

Next, the operation of the configuration shown in FIGS. 1 and 2 will be described in detail with reference to FIG. In FIG. 3, S1 reads an instruction. This corresponds to the I-UNIT issuing the instruction read request IU-REQ to the S-UNIT, and S
-UNIT reads the instruction from CHE (cache memory) and passes it to I-UNIT.

S2 is TL as the instruction passed in S1.
For example, SSK or IPTE which is a B entry erasing command is executed. Corresponding to this, SSK and I
Notify PTE to MCU.

In step S3, corresponding to step S2, the MCU requests the S-UNITs of all CPUs to execute BI through the route of FIG. 2 (requests the invalidation request BI-REQ). The S-UNIT receiving this invalidation request BI-REQ is (B) in FIG.
Register OI that already configures register 1 by the determination unit of
-If the signal indicating that the target address (real address) of the partial purge is valid of "PPAR0-VLD" and "OI-PPAR1-VLD" is "up to the second", proceed to S4 and select "2 When it is "visible," go to S5, and when "from the third", S
Proceed to 7.

S4 is a register OI-PPA in S-UNIT.
Of the two R0-VLD and OI-PPAR1-VLD, the signal indicating that the target address (real address) of the partial purge is valid is set to "up to the second", that is, the address is valid. Since one or two signals have been set, the partial purge control unit 2 of FIG.
Is issued to partially purge the TLB (invalidate the corresponding entry). And the corresponding register OI-PPAR0-V
Clears (disables) the signal that indicates that the address set in LD and OI-PPAR1-VLD is valid.

S5 is a register OI-PPA in S-UNIT.
Of the two R0-VLD and OI-PPAR1-VLD, the signal indicating that the target address (real address) of the partial purge is valid "became the second", so that The determination unit 5 issues an instruction suppression request + INH-IU-REQ and suppresses acceptance of a new instruction read request from the I-UNIT. This allows
Make sure that no new BI-REQ is generated and the TLB is not completely purged. While issuing this command suppression request + INH-IU-REQ and suppressing the reading of new commands,
When the partial purge of the LB is executed, the instruction suppression request + INH-IU-REQ is released in S6, and the process proceeds to S1.

S7 is a register OI-PPA in S-UNIT.
A signal indicating that the target address (real address) of the partial purge is valid has already been set in two of R0-VLD and OI-PPAR1-VLD, and "from the third" of Fig. 1 (b). When the determination unit 5-4 of 4 sets the register CHG-TO-PTLB of (a) of FIG. 1 by + SET-CHG-TO-PTLB, the all purge control unit 4 issues the all purge request + PT-REQ. Then, all entries in the TLB are invalidated (all purges are performed).

From the above, the register 1 of FIG.
Registers that make up OI-PPAR0-VLD, OI-PPAR1-VLD
When two signals indicating that the address of the partial purge target is valid are set here, in order to prevent the reading of a new instruction in S5, the entire purge is prevented from occurring and the partial purge is performed in the meantime. By restarting the reading of a new instruction after the execution, it is possible to prevent the TLB from being completely purged and to efficiently use the TLB.

Incidentally, FIG. 1A of the embodiment described above,
In (b), it was explained that two signals indicating that the target address of the partial purge is valid can be set in the register 1. However, three signals, that is, a larger number of addresses are valid. Even if it is possible to set the signal indicating that the maximum number of addresses is valid, the signal indicating that the maximum number of addresses is valid is set (or the invalidation request BI-REQ has already been issued and the target address of partial purge existing in the pipeline When a signal indicating that a valid address signal is set (a signal indicating that the maximum number-predetermined number) is valid is set, the reading of a new instruction is suppressed. May be.

[0035]

As described above, according to the present invention,
Since a configuration is adopted in which the reading of a new instruction is suppressed when the address to be the target of the partial purging of the TLB reaches a predetermined value (for example, the maximum number) that can be held, the entire purging of the TLB is avoided and the relevant TLB is avoided. Can be used efficiently and address translation can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an explanatory diagram of a conventional technique.

[Description of Reference Signs] 1: Register for setting a signal indicating that an address to be partially purged is valid 2: Partial purge control unit 3: Register 4: All purge control unit 5, 5-1 to 5-4 : Judgment part

Claims (1)

[Claims] 1. A partial purge processing method for partial purging of a TLB, which holds a predetermined number of signals indicating that an address targeted for partial purging is valid in response to a TLB invalidation request BI-REQ. A register (1) and a partial purge control unit (2) that issues a partial purge request SR-REQ when a signal indicating that the address to be partially purged is valid is held in the register (1). , It is determined whether or not the number of signals indicating that the target address of the partial purge that can be held in the register (1) is valid has reached a predetermined value (for example, the maximum value), and when the predetermined value is reached, The instruction read suppression request INH-IU-REQ is issued, and a signal indicating that the target address of the partial purge is valid is set in the register (1). When the partial purge control unit (2) issues a partial purge request SR-REQ to perform the partial purge of the TLB, the determination unit (5) sets the register (1) to a predetermined value (for example, the maximum number). Is configured to issue a command read inhibition request INH-IU-REQ to inhibit the reading of a new instruction when it is determined that the signal indicating that the target address of the partial purge is set is valid. Partial purging method of TLB, characterized by: