JP3088293B2 - Cache memory storage consistency control device and storage consistency control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory storage consistency control apparatus and method in a multiprocessor system each including a plurality of processors each having a cache memory.

[0002]

2. Description of the Related Art Conventionally, this type of cache memory control system reduces the operation rate of a common bus while improving data matching between cache memories and main memories of each processor in a multiprocessor system, thereby improving system performance. It is used for the purpose.

For example, as disclosed in Japanese Patent Application Laid-Open No. 2-226449, a main storage area is divided into a processor-specific use area and a shared area, and when a write access request destination from the processor is not the main storage shared area, Switches from write-through cache memory control to write-back cache memory to prevent unnecessary write operations to the main memory and unnecessary tag checks of other processors.

Further, as shown in Japanese Patent Application Laid-Open No. Hei 4-291642, an independent bus dedicated to a cache memory is set separately from a common bus connected to a main memory, and data which does not exist in its own cache memory is stored in another bus. , The relevant data is read from another cache memory through a cache dedicated bus.

[0005]

In the conventional cache memory control system described above, an operation for determining whether or not there is an access to the inter-processor shared area that requires the cache coherence control is required for every memory access. In addition, since it is necessary to perform an operation of checking whether or not data that does not exist in its own cache memory exists in another cache memory, the memory access operation of the multiprocessor system is slower than that of the uniprocessor system. There is a first problem.

Further, in the case of memory access to an inter-processor shared area requiring cache coherence control, is there data to be used in another cache memory using a common bus connecting all processors and main memory? Even if a cache-only bus is provided, the data request from each cache memory to another cache memory overlaps and the operation rate of the cache-only bus increases, so the operation of the common bus that connects the main memory and each processor There is a second problem that the rate is high, memory access takes time, and performance in proportion to the number of connected processors cannot be obtained.

SUMMARY OF THE INVENTION It is an object of the present invention to separately set an instruction for accessing non-shared data and an instruction for accessing shared data, and to omit a cache matching process for an instruction for accessing non-shared data. The cache match judgment operation, which the hardware independently performed for all memory accesses, is performed only for the memory access by the instruction for accessing the shared data, thereby speeding up the normal memory access processing. When writing, the processor number and write address are recorded.When reading shared data, it is determined whether or not there is an overlap with the recorded write address. Data is read from the memory, and if there is an overlap, the processor number of the overlapped processor number is read. By reading data from the cache memory corresponding to the cache memory, there is no inquiry to all other cache memories that use the bus, suppressing the occupancy of the bus for cache matching processing, and using the bus for normal memory access. It is an object of the present invention to provide a storage consistency control method of a cache storage consistency control device that can achieve high speed without hindrance.

[0008]

According to the present invention, there is provided a memory coherence control apparatus for a cache memory in a multiprocessor system including a plurality of processors each having a cache memory and a main memory shared by the processors. A storage control unit to which all the cache memories are connected, wherein the storage control unit holds and reduces and adds a write processor number and a write access address in units of a cache synchronous write request; A match processing determining mechanism for determining whether cache matching processing is necessary or not based on the overlap between the write access address and the synchronous read address, and reading cache synchronous read data from the write processor number in response to the match processing determination result Characterized by having a cache memory controller to copy the data into the cache memory on the read processor determines the cache memory.

A method according to the present invention is a multiprocessor system comprising a plurality of processors each having a cache memory and a main memory shared by the processors, wherein the cache memories are all connected. In the cache memory storage consistency control method in a system provided with a mechanism, when a processor executes a cache synchronous write instruction to update data shared by the plurality of processors, a request transmitted through the cache memory is storage coherency control mechanism registers hold the processor number and write access address for performing cache synchronous writes as a set, requests from the key Yasshi Yumemori cash synchronous write command to be executed by any of the processors The read access to the relative cache deletes the synchronous write access address matching registered the write access address and the registered processor number, any requests from key Yasshi Yumemori Cash synchronous read instructions to be executed by processor It is determined whether or not the address overlaps with the registered write access address. If the address does not overlap, the data on the main memory is fetched as read data, and if there is an overlap, the cache belonging to the processor of the corresponding registered processor number It is characterized in that the relevant data is taken out as read data from the memory.

[0010]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an example of a multiprocessor system to which the present invention is applied. The multiprocessor system includes two CPUs 1 and 2, cache memories 3 and 4 corresponding to the CPUs 1 and 2, a storage control unit 5, and a main memory 6, and the cache memories 3 and 4 and the storage control unit 5 And the main memory 6 are connected by a system bus 7.

CPUs 1 and 2 perform cache synchronous reading,
Each instruction of cache synchronous write, cache asynchronous read and cache asynchronous write is executed, and a memory access request is sent to the main memory 6 and the storage control unit 5 via the cache memories 3 and 4. The cache memories 3 and 4 receive a memory access request from the CPUs 1 and 2, and in the case of cache asynchronous read or cache asynchronous write, perform data transfer only by control in their own cache memory, and perform cache synchronous read or cache synchronous write. In this case, a memory access request is sent to the storage control unit 5. The storage control unit 5 receives these cache synchronous memory access requests from the cache memories 3 and 4. The main memory 6 receives a memory access request from the cache memories 3 and 4 regardless of whether the cache is synchronous or asynchronous.

FIG. 1 shows the details of the storage control unit 5.
The storage control unit 5 has, for each cache synchronous write request, a processor number storage area 10 for storing a write processor number and a write access storage area 11 for holding a write access address as a set. Matching processing determining mechanism 12 that determines whether cache matching processing is necessary or not based on the overlap between the write access address in the write access address storage area 11 and the cache synchronous read address.
And a cache memory control mechanism 13 for copying the storage contents of the cache memory corresponding to the processor number in the write processor number storage area 10 to the cache memory of the cache synchronous read processor according to the match determination result.
have.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described in detail with reference to FIG. At the time of data access that does not consider data sharing between CPUs (software recognizes whether or not to consider it), the CPU sends an asynchronous read instruction or write instruction to the corresponding cache memory, and the CPU shares data. At the time of data access taking into account the above, a cache synchronous read or cache synchronous write instruction is sent to the corresponding cache memory.

In the case of non-shared data, if the requested data is in the cache memory, the data is fetched from the cache memory or the data is stored in the cache memory. However, if the requested data is not in the cache memory, a cache miss occurs. At that time, the block containing the requested data is transferred from the main memory to the cache memory. Thereafter, the operation is performed in the same manner as when data exists in the cache memory. In this data access operation, the operation is performed without data sharing. Therefore, it is necessary to determine whether a block corresponding to the cache memory connected to another CPU exists and to control the cache memory for matching the memory when the block exists. Not done.

On the other hand, when data sharing between CPUs is taken into consideration, a cache synchronous write command is sent to the storage control unit 5 through the cache memory. The storage control unit 5 stores the write requested address and the requested processor number in the write access address storage area 11 and the processor number storage area 1.
Register to 0. At this time, if there is an item already stored at the same address, it is deleted (100, 100 in FIG. 3).
101), the latest write processor number is registered (102, 103). The write data is store in the cache memory corresponding to the request CPU (104). In the cache synchronous read command, the command is sent to the storage control unit 5 through the cache memory. The storage control unit 5 determines whether overlaps comparing registered Rokuzumi A Dore scan and read request address of the write access address vault 11 or al a match processing determination mechanism 12 (110 in FIG. 4).

The judgment result is the cache memory control mechanism 13
When there is no overlap, the block containing the requested data is transferred from the main memory to the cache memory, similarly to the cache miss in the case of non-shared data (11).
1). Thereafter, the operation is the same as when data exists in the cache memory.

If there is an overlap, the processor number corresponding to the write access address where the overlap is detected is taken out from the processor number storage area 10 and inputted to the cache memory control mechanism 13. The cache memory control mechanism 13 retrieves a block containing the requested data from the cache memory corresponding to the input processor number and transfers it to the cache memory of the read destination (11).
2). Thereafter, the operation is the same as when data exists in the cache memory.

When the processor number for which the overlap is detected is the same as the processor number for executing the cache synchronous read instruction, the operation is performed without a data transfer between cache memories as a cache hit. When the processor number storage area 10 and the write access address storage area 11 are full, one registered item is deleted and new registration is performed (103). The deletion information is stored in the cache memory control mechanism 13
And the data block of the cache memory of the processor number corresponding to the deleted item is returned to the main memory.

FIG. 5 shows an embodiment of the storage control unit 5. The storage control unit 5 includes a random access memory (RAM) 32 for storing a write processor number for each cache synchronous write request, and a random access memory 33 for storing a write access address.
And a RAM control unit 31 for controlling address designation and writing / reading of the RAM 32 and the RAM 33, and a comparison for judging the necessity of the cache matching process due to the overlap between the write access address of the RAM 33 and the cache synchronous reading address at the time of cache synchronous reading Container 34
In response to the match detection signal from the comparator 34,
And a cache memory control unit for copying data stored in the cache memory corresponding to the processor number output from the cache memory to the cache memory of the synchronous read processor.

The CPU sends a normal read command or a write command to the corresponding cache memory for data access that does not consider data sharing between the CPUs (the software recognizes whether or not to consider the data sharing). A cache synchronous read or cache synchronous write command is sent to the corresponding cache memory when data is considered for sharing.

When data sharing between CPUs is considered, a cache synchronous write command is sent to the storage control unit 5 through the cache memory. The storage control unit 5 registers the address requested to be written by the RAM control unit 31 and the processor number requested to be written in the free areas of the RAM 33 and the RAM 32.

At this time, if there is an item already stored at the same address by the RAM control unit 31, it is deleted and the latest write processor number is registered.
The write data is stored in the cache memory corresponding to the request CPU. In the cache synchronous read command, the command is sent to the storage control unit 5 through the cache memory. In the storage control unit 5, the RAM 33
The comparator 34 compares the registered address and the read request address with each other to determine whether or not they overlap.

Under the control of the RAM control unit 31, this determination operation is performed for all registered entries in the RAM 33. The coincidence detection signal is input to the cache memory control unit 35, and when there is no overlap, similarly to a cache miss in the case of non-shared data, a block containing requested data is transferred from the main memory to the cache memory. Thereafter, the operation is the same as when data exists in the cache memory. If there is an overlap, the processor number corresponding to the updated access address where the overlap is detected is input to the cache memory control unit 35 extracted from the RAM 32.

The cache memory control unit 35 fetches a block containing the requested data from the cache memory corresponding to the input processor number, and transfers the block to the read-destination cache memory. Thereafter, the operation is the same as when data exists in the cache memory. When the processor number for which the overlap is detected is the same as the processor number for executing the cache synchronous read instruction, the operation is performed without a data transfer between the cache memories as a cache hit.

When the RAM 32 for storing the processor number and the RAM 33 for storing the updated access address run out, one registered item is deleted and new registration is performed. The deletion information is input to the cache memory control unit 35, and the cache memory data block of the processor number corresponding to the deletion item is returned to the main memory.

FIG. 6 shows a second embodiment of the present invention.
Shown in In this embodiment, the processor number storage area 10 in the storage control unit 5 is omitted from the first embodiment. The cache synchronous write operates in the same manner as the first embodiment except that the registration of the write requesting processor number in the processor number storage area is no longer performed.

In the cache synchronous reading, the coincidence processing judging mechanism 52 judges the overlap between the write access address and the read address in the write access address storage area 51. If there is no overlap, the same operation as in the first embodiment is performed. When there is an overlap, the processor number of the overlap cannot be identified. Therefore, the cache memory control mechanism 53 inquires whether or not there is a data block including the requested address in all the other cache memories. After the memory is determined, the data block is transferred from the cache memory to the requesting cache memory. The other operations are the same as those in the first embodiment.

By providing the means for controlling as described above, the memory matching control can be performed. In the second embodiment, the speed of the asynchronous memory access is increased as in the first embodiment, and the amount of hardware is reduced by eliminating some functions from the first embodiment. It has the effect that can be done.

[0030]

A first effect of the present invention is that the memory access operation of the multiprocessor system is faster as in the case of the single processor system. The reason is that, in the present invention, an operation for determining whether or not an access is made to an inter-processor shared area that requires cache coherence control is performed only by a specific memory access instruction. Another reason is that it is no longer necessary to perform an operation of checking each of the other cache memories whether data that does not exist in its own cache memory exists in another cache memory.

A second effect is that the operating rate of the common bus connecting the main memory and each processor in the multiprocessor system is reduced, the time for memory access is shortened, and a performance proportional to the number of connected processors can be obtained. It has become. The reason is that, in the present invention, in a memory access to an inter-processor shared area that requires cache coherency control, data used for all other cache memories is shared using a common bus connecting all processors and main memory. This is because there is no need to inquire whether or not the storage exists, and the storage control unit performs the coincidence determination collectively.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a storage control unit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a multiprocessor system to which the present invention is applied.

FIG. 3 is a flowchart showing an operation at the time of cache synchronous writing in the present invention.

FIG. 4 is a flowchart showing an operation at the time of cache synchronous reading in the present invention.

FIG. 5 is a diagram showing an embodiment of a storage control unit according to the present invention.

FIG. 6 is a diagram showing another embodiment of the storage control unit according to the present invention.

[Explanation of symbols]

 1, 2 CPU 3, 4 Cache memory 5 Storage control unit 6 Main memory 7 System bus 10 Processor number storage area 11 Write access address storage area 12 Matching processing determination mechanism 13 Cache memory control mechanism 31 RAM control unit 32 Random access memory 33 Random Access memory 34 Comparator 35 Cache memory control unit 51 Write access address storage area 52 Matching processing determination mechanism 53 Cache memory control mechanism

──────────────────────────────────────────────────続 き Continued from the front page (56) References JP-A-8-6855 (JP, A) JP-A-6-44136 (JP, A) JP-A-5-108578 (JP, A) JP-A-4- 245350 (JP, A) Ben Catanzazzo, "SPARC Multiprocessor Architecture", First Edition, ASCII, May 1, 1995, p. 173-178 Yoshizo Takahashi, "Parallel Processing Mechanism", Maruzen Co., Ltd., August 25, 1989, p. 186 -199 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/12

Claims (3)

(57) [Claims] 1. A storage control unit for a cache memory in a multiprocessor system including a plurality of processors each having a cache memory and a main memory shared by the processors, wherein the storage control unit is connected to all the cache memories. The storage control unit comprises: a mechanism for holding and reducing and adding a write processor number and a write access address for each cache synchronous write request; and an overlap between the held write access address and the synchronous read address at the time of cache synchronous read. A matching processing determining mechanism for determining whether or not cache matching processing is necessary, and in response to the matching processing determination result, determining a cache memory from which the cache synchronous read data is to be read based on the write processor number and reading the cache memory. Storage coherency control unit in the cache memory, characterized in that it comprises a cache memory controller to copy the data into the cache memory on the processor and. 2. A multiprocessor system comprising a plurality of processors each having a cache memory and a main memory shared by the processors, wherein a cache memory storage consistency control mechanism to which all the cache memories are connected is provided. A cache memory storage consistency control method in a system, comprising: a cache memory storage consistency control mechanism for a request transmitted through a cache memory when a processor executes a cache synchronous write instruction to update data shared by a plurality of processors. Registers and holds a processor number and a write access address that perform cache synchronous writing as a set, and stores the key by a cache synchronous write instruction executed by any of the processors.
Remove the registered processor number and registered the write access address matches the cache synchronization write access address to request from Yasshi Yumemori, requests from key Yasshi Yumemori Cash synchronized reading instructions executed by any of the processors To determine whether the read access address overlaps with the registered write access address,
If the data does not overlap, the data on the main memory is taken out as read data. If there is an overlap, the data is taken out as read data from the cache memory belonging to the processor of the corresponding registered processor number. Match control method. 3. A storage control unit for a cache memory in a multiprocessor system having a plurality of processors each having a cache memory and a main storage shared by the processors, wherein the cache memories are all connected. The storage control unit includes a mechanism for holding, deleting, and adding a write access address in units of cache synchronous write requests, and a cache match based on an overlap between the held write access address and the synchronous read access address during cache synchronous read. or comprising a matching process determination mechanism determines Yes No processing, when there overlapping said a match processing determination result, there is a data block including the read request access address data to all other cache memory A storage consistency control device for a cache memory, which inquires whether the data is present and, if the data is present, retrieves the data as read data for cache synchronous reading.