JPS57203157A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57203157A
JPS57203157A JP8917281A JP8917281A JPS57203157A JP S57203157 A JPS57203157 A JP S57203157A JP 8917281 A JP8917281 A JP 8917281A JP 8917281 A JP8917281 A JP 8917281A JP S57203157 A JPS57203157 A JP S57203157A
Authority
JP
Japan
Prior art keywords
memory unit
data
processing
access
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8917281A
Other languages
Japanese (ja)
Other versions
JPS6112305B2 (en
Inventor
Isao Yamazaki
Katsuhiro Matsukawa
Kiyokazu Hanatani
Fumiaki Seto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8917281A priority Critical patent/JPS57203157A/en
Publication of JPS57203157A publication Critical patent/JPS57203157A/en
Publication of JPS6112305B2 publication Critical patent/JPS6112305B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce a load on a processing control unit by enabling a multiprocessor type data processing unit to operate by setting operation parameters during the fetching and accessing of data to be processed at a time. CONSTITUTION:Memory unit addresses during data transfer between processing units PU1-PUn, and a memory unit 2 are transferred from a processing control unit 4 prior to the start of processing and then set it an address register 14. Address data during access to the memory unit 2 are read out of the address register 14 corresponding to processing units PU1-PUn permitted to access the memory unit 2, and then sent out to the memory unit 2. The data of a register 16 are used to decide on which data in a couple of registers of the address register 14 is used for the access. Becuase of this control structure, access control parameters to the memory unit 2 are processed at a time by being specified in the register 16.
JP8917281A 1981-06-10 1981-06-10 Data processor Granted JPS57203157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8917281A JPS57203157A (en) 1981-06-10 1981-06-10 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8917281A JPS57203157A (en) 1981-06-10 1981-06-10 Data processor

Publications (2)

Publication Number Publication Date
JPS57203157A true JPS57203157A (en) 1982-12-13
JPS6112305B2 JPS6112305B2 (en) 1986-04-07

Family

ID=13963363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8917281A Granted JPS57203157A (en) 1981-06-10 1981-06-10 Data processor

Country Status (1)

Country Link
JP (1) JPS57203157A (en)

Also Published As

Publication number Publication date
JPS6112305B2 (en) 1986-04-07

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