JPH08106417A - Memory access method and memory sharing system - Google Patents

Abstract

PURPOSE: To enable access in a short time even when a cache memory is mishit. CONSTITUTION: The memory sharing system is equipped with the cache memory 2a having a bus snoop function for monitoring access from other bus masters to a common memory 5 and a copying-back function for performing the rewriting of the common memory 5 later, and has a CPU 2 which starts evaluating the contents of the cache memory 2a and contents that other bus masters try to read out when request to read the common memory 5 that are made by other bus masters are detected, and a control circuit 7 which makes the common memory 5 begin to be read out when other bus masters 3 makes the requests to read the common memory 5, and transfers the contents of the common memory 5 that begins to be read to other bus masters when the cache memory 2a is mishit or transfers the contents of the cache memory 2a itself to other bus masters when the cache memory is hit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a memory access method in a memory sharing system having a plurality of processors and a shared memory, and a memory sharing system suitable for realizing such a memory access method.

[0002]

2. Description of the Related Art A cache memory is physically added to a CPU and functionally functions as an extension of main storage means. Further, the cache memory is mechanically an associative memory, that is, an address and its contents are paired and stored.

The reference to the main storage means having the cache memory is performed as follows. The final address is created. That address is sent to the cache memory.

In the case of reading from the main storage means, the cache memory searches the stored contents based on the address. If the address does not exist, the contents are taken out from the main storage means and stored in the cache memory together with the address as a pair. Data transfer between main memory and cache memory is 8 words,
It is made in units of blocks such as 16 words.
This is because when a certain word is referenced, there is a very high probability that a word in the vicinity thereof will be referenced. If there is no free space in the cache memory, some block needs to be flushed, but basically LRU (least recently used:
A method of managing so that the most recent time used last) is used.

In the case of writing to the main storage means,
If the address exists in the cache memory, both the cache memory and the main memory are rewritten, and if the address does not exist in the cache memory, only the main memory is rewritten.

All the above steps (1) to (3) are automatically performed by hardware. Therefore, even a machine language program does not differ depending on whether or not a cache memory exists.

In the above description, the writing is performed by a method called "write through", and the main storage means is always rewritten at the time of writing. For this reason, there is no change in the write time, so there is no improvement in performance, but the read time is shortened and the performance is improved. In many programs, reading is more frequent than writing, and since the cache memory is faster than the main storage means, the effect of the cache memory becomes remarkable by shortening the reading time.

On the other hand, write after (write afte)
There is a method called r) or copy back. This method, in the case of the above-mentioned writing,
When data exists in the cache memory, it is rewritten only in the cache memory. Then, the content of the cache memory is referenced at an appropriate timing to rewrite the main storage means. By doing so, the writing time can be shortened and the performance can be improved.

That is, the copy-back method has an advantage that the bus is used less frequently. This is effective when a plurality of bus masters share the bus, such as a multiprocessor system or a system using a plurality of DMA controllers.

The copyback method is also effective when there is no other bus master candidate. If the write operation to the main storage means continues, the access to the main storage means becomes a bottleneck in the write-through method. In contrast,
If the copy-back method is adopted, bus access is required only when updating the main storage means. Therefore, the frequency of bus access is reduced, and the write operation to the main storage means does not hinder the pipeline operation.

[0011]

However, a plurality of CPUs are required.
When any of the CPUs has a cache memory in the multiprocessor system having the above, the control becomes complicated in this copyback system.

That is, coherency (coherency) between the shared memory and the cache memory forming the main memory means.
y: Consistency) must be maintained. The function of monitoring so as to maintain such coherency is called a bus snoop function (or bus snooping).

The bus snoop function will be described with reference to FIGS. 5 and 6. I am the bus master (bus
A CPU (hereinafter simply referred to as a CPU) 2 having a cache memory although it is not a master) always monitors an address signal and a control signal (for example, write / read signal) of the bus 1.

The CPU 2 has already rewritten the data in the shared memory 5, and the rewritten data is stored in the cache memory 2a.
Has not been written back (updated) yet.

In this state, the CPU 2 sets the memory inhibit (MI) signal to the active state (shown in FIG. 6 for the case of low active) (FIG. 6 (b)), and another bus master. Reading of the shared memory 5 from 3 is prohibited.

Another CPU in the bus master state (simply referred to as another bus master; it does not matter whether or not it has a cache memory) 3 tries to access (here, consider reading) the shared memory 5. 6 (a)
), The CPU 2 fetches the address signal, and CP
It is evaluated by comparing with the tag part of the cache memory built in U (tag: a character attached to a set of data, which includes information about this set and can be identified).

Then, when the result of the evaluation is a mishit (when the comparison between the address and the tag does not match), the MI signal of the shared memory is stopped (here, high).
Then, generation of a read address (FIG. 6C), memory read (FIG. 6D), transfer to the buffer 6 for timing adjustment (FIG. 6E), transfer from the buffer 6 to the bus 1 Transfer (FIG. 6 (f)) is performed. And CP
U2 is the TA signal (Data Acknowledgment).
ge) signal) becomes active (FIG. 6 (g)), the other bus masters 3 send the buffer 6 sent to the bus 1
Read the stored contents of.

When there is a hit (when the comparison between the above address and the tag matches), the contents of the cache memory of the CPU are transferred to the bus 1 while the shared memory is locked.
The other bus master 3 reads this.

In such an operation, other processing cannot be executed during the cache memory evaluation processing.
If the cache memory hits, no problem occurs due to high-speed reading of the cache memory, but if there is a miss hit, it takes a lot of time to start accessing the shared memory (start reading the shared memory) after the evaluation. Will be required. In this way, when the cache memory has a mihit, in the memory sharing system having the configuration shown in FIG. 5, when the above-described operation occurs, the operations of (a) to (g) of FIG. 6 are sequentially performed. Because
It takes a lot of time.

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory sharing system including a CPU having a copy-back type cache memory and a memory shared by other bus masters. Provided is a memory access method and a memory sharing system in which another bus master can read in a short time even if a cache memory of a CPU misses when a read request is made to the shared memory from another bus master. It is to be realized.

[0021]

A first means for solving the above problems is a cache having a bus snoop function for monitoring access to a shared memory from another bus master and a copyback function for rewriting the shared memory. In a memory access method in a system including a CPU provided with a memory and a shared memory shared by the CPU and another bus master, when a read request to the shared memory from another bus master is detected, In addition to prohibiting reading from the shared memory of other bus masters, the contents of the cache memory and the contents that other bus masters tried to read are evaluated, and the contents that other bus masters tried to read are written to the shared memory. The read was started, and the evaluation resulted in a cache memory miss-hit. The case transfers the contents of the shared memory that start reading to another bus master, if the cache memory is hit is a memory access method characterized by transferring the contents of the cache memory to another bus master.

A second means for solving the above-mentioned problems is CP
U and a shared memory shared by other bus masters, and a cache memory having a bus snoop function for monitoring access from other bus masters to the shared memory and a copyback function for rewriting the shared memory later, When a read request from the bus master to the shared memory is detected, the read from the shared memory of other bus masters is prohibited, and the contents of the cache memory and the contents that the other bus master tried to read are evaluated. When there is a read request from the CPU to be started and another bus master to the shared memory, the shared memory starts to read the content that the other bus master was trying to read, and the evaluation result is received from the CPU. , When the cache memory is a mishit, read is started The content of organisms memory is transferred to another bus master, if the cache memory is hit is a memory sharing system characterized by and a control circuit for transferring the contents of the cache memory to another bus master.

A third means for solving the above problems is CP
U and a shared memory shared by other bus masters, and a cache memory having a bus snoop function for monitoring access from other bus masters to the shared memory and a copyback function for rewriting the shared memory later, When a read request from the bus master to the shared memory is detected, the read from the shared memory of other bus masters is prohibited, and the contents of the cache memory and the contents that the other bus master tried to read are evaluated. Regarding the CPU to start, the buffer that temporarily holds the contents read from the shared memory, and the contents that other bus masters tried to read when there was a read request from another bus master to the shared memory Move from shared memory to read buffer
In response to the evaluation result from, the control circuit transfers the contents of the buffer to another bus master if the cache memory has a miss hit, and transfers the contents of the cache memory to another bus master if the cache memory has a hit. And a memory sharing system characterized by including

[0024]

In the memory access method as the first means for solving the problem, when a read request from the other bus master to the shared memory is made, the CPU having the copy-back type cache causes the other bus master to the shared memory. Access is prohibited, and generation of an address to the shared memory and evaluation of the cache memory of the CPU are simultaneously started. Then, depending on the result of the cache memory evaluation, the contents of the cache memory or the contents of the shared memory are transferred to another bus master.

In the memory sharing system which is the second means for solving the problem, when a read request from another bus master to the shared memory is made, the CPU having the copy-back type cache operates as a bus master for the shared memory. Access is prohibited, and evaluation of the cache memory of the CPU is started at the same time. The control circuit also generates an address for reading and initiates reading the contents of the shared memory during cache memory evaluation. Then, depending on the result of the cache memory evaluation, the contents of the cache memory or the contents of the shared memory that started reading are transferred to another bus master via the bus.

In the memory sharing system which is the third means for solving the problem, when a read request from another bus master to the shared memory is made, the CPU having the copy-back type cache operates the other bus master to the shared memory. Access is prohibited, and evaluation of the cache memory of the CPU is started at the same time. The control circuit also generates an address for reading. Then, while the cache memory is being evaluated, the contents of the shared memory are transferred to the buffer.
Then, depending on the result of the cache memory evaluation, the contents of the cache memory or the contents of the buffer are transferred to another bus master via the bus.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a time chart showing a processing procedure at the time of a cache miss hit of the memory access method of one embodiment of the present invention, and FIG. 2 shows a processing procedure at the time of a cache hit of the memory access method of one embodiment of the present invention. FIG. 3 is a time chart, and FIG. 3 is a configuration diagram showing a schematic configuration of a memory sharing system according to an embodiment of the present invention.

First, the configuration of a memory sharing system according to an embodiment of the present invention will be described with reference to FIG. Various processors, controllers, memories and the like are connected to the bus 1 to exchange data and various access request signals.
The CPU 2 is a processor having a cache memory 2a controlled by the copy back method, and is connected to the bus 1. The other bus master 3 is a processor (whether or not it has a cache memory) connected to the bus 1 or various controllers (DMA controller,
SCSI controller, LAN controller, etc.), and is a bus master that issues an access request to the shared memory in this embodiment. The shared memory 5 is accessed by the processor and various controllers connected to the bus 1. The buffer 6 is for temporarily holding the data read from the shared memory 5 when the processor fetches the data. The control circuit 7 is connected to the bus 1 and performs various controls (cache memory control, memory control).

With respect to the operation of the memory sharing system and the procedure of the memory access method of the present embodiment thus configured, referring to the time chart of FIG. 1, the configuration diagram of FIG. 3 and the explanatory diagram of FIG. The case will be described.

The CPU 2 has already rewritten the data in the shared memory 5, and the rewritten data is stored in the cache memory 2a.
Has not been written back (updated) yet.

The CPU 2 has a bus snoop function and constantly monitors the address signal and control signal (for example, write / read signal) of the bus 1. In this state, the Memory Inhibit
(MI)) signal in an active state (shown in FIG. 1 in the case of low active) (see FIG.
(B) and FIG. 4 (b), reading of the shared memory from other bus masters 3 is prohibited.

When there is a read request (FIG. 1 (a), FIG. 4 (a)) from another bus master 3, evaluation of the cache memory is started. Further, at the same time, the control circuit 7 generates an address whose content is to be read by another bus master 3 and supplies it to the shared memory 5 (see FIG. 1).
(C), FIG. 4 (b)).

As a result, even if the CPU 2 is in the cache memory evaluation state and the other bus masters 3 are prohibited from accessing the shared memory, the control circuit 7 gives an instruction to read from the shared memory 5. Is started (FIG. 1 (d), FIG. 4 (c)).

That is, since it takes a certain amount of time to evaluate the cache memory, during this time, the memory is read and the buffer is written (see FIGS. 1B and 4).
(C)) is performed.

When the cache memory is evaluated to be a mishit, the CPU 2 negates the MI signal.
gate: stop) (Fig. 1 (b) '). Here, the control circuit 7 receives the data read from the shared memory 5 in response to the fact that the MI signal is negated while the data acknowledge signal (referred to as TA signal) is not yet output from the CPU 2. The data is latched in the buffer 6 (FIGS. 1E and 4C), and the data latched in the buffer 6 is output to the bus 1 (FIGS. 1F and 4D).

When the CPU 2 activates the TA signal (FIG. 1 (g)), the other bus master 3 reads the contents held in the buffer 6 sent to the bus 1. By performing the above-described operation, the preparation for reading the shared memory is performed in parallel with the evaluation of the cache memory, so that the operation time when the cache memory misses is shortened. In particular, the time corresponding to the read access to the shared memory can be saved. The data transmission from the buffer 6 to the bus 1 is performed in an extremely short time as compared with the reading from the shared memory 5.

In a system in which the evaluation time and the time required for reading from the shared memory are close to each other, a buffer for temporarily holding the read contents of the shared memory is not used and evaluation is being performed (for example, at the same time as the start of evaluation). To start reading, transfer the data read from the shared memory to another bus master at the time of a miss, and
It is also possible to invalidate reading from the shared memory and transfer the cache contents to another bus master upon hit.

When such an operation was confirmed by an experiment, it was possible to shorten the time corresponding to about 30 to 40% of the total operation time when the cache memory missed.

The case where the cache memory is hit is shown in the time chart of FIG. 2, and it is the same until the read data from the shared memory is moved to the buffer 6 (FIG. 2 (e)). When the cache memory is hit as a result of the evaluation, the CPU 2 activates the TA signal while keeping the MI signal active (FIG. 2 (g)).
′), Put contents of cache memory onto bus 1.

Then, the other bus master 3 reads the contents held in the cache memory sent to the bus 1. The operation at the time of the cache hit is the same as that at the time of the conventional cache hit, and the operation time is also the same.

As described in detail above, a CPU having a cache memory having a bus snoop function for monitoring access to a shared memory from another bus master and a copy back function for rewriting the shared memory, and these CPUs and In a memory access method in a system having a shared memory shared by another bus master, when a read request from the other bus master to the shared memory is detected, the read from the shared memory of the other bus master is performed. In addition to prohibiting, evaluate the contents of the cache memory and the contents that the other bus master tried to execute the read, and start the reading to the shared memory for the contents that the other bus master tried to execute the read,
If the cache memory misses as a result of the evaluation, the contents of the shared memory that started reading are transferred to another bus master, and if the cache memory hits, the contents of the cache memory are transferred to another bus master. In the memory access method, the read of the contents of the shared memory is started during the evaluation of the cache memory, and the contents of the shared memory that has started the read are transferred to another bus master at the time of a miss hit. The read time from other bus masters is shortened even when the memory is hit.

A shared memory shared by the CPU and other bus masters, a bus snoop function for monitoring access from other bus masters to the shared memory, and a copyback function for rewriting the shared memory later. When it has a memory and detects a read request from another bus master to the shared memory, it prohibits the read from the other bus master's shared memory and tries to execute the contents of the cache memory and the other bus master. CPU to start evaluation with contents
Then, when there is a read request from the other bus master to the shared memory, the shared memory starts reading the content that the other bus master was trying to read,
In response to the evaluation result from the CPU, if the cache memory has a mishit, the contents of the shared memory that has started reading are transferred to another bus master, and if the cache memory has a hit, the contents of the cache memory are changed to another. In a memory sharing system characterized by including a control circuit for transferring to the bus master, the reading of the contents of the shared memory is started during the evaluation of the cache memory, and at the time of a miss hit, the reading of the shared memory Since the contents are transferred to another bus master, the read time from another bus master is shortened even when the cache memory misses.

A shared memory shared by the CPU and other bus masters, a bus snoop function for monitoring access from other bus masters to the shared memory, and a cache having a copyback function for rewriting the shared memory later. When it has a memory and detects a read request from another bus master to the shared memory, it prohibits the read from the other bus master's shared memory and tries to execute the contents of the cache memory and the other bus master. CPU to start evaluation with contents
And a buffer that temporarily holds the contents read from the shared memory, and the contents that other bus masters tried to read when there was a read request from the shared memory to the shared memory. Move to the read buffer, receive the evaluation result from the CPU,
A control circuit for transferring the content of the buffer to another bus master when the cache memory has a mishit, and for transferring the content of the cache memory to another bus master when the cache memory has a hit. In the memory sharing system, the contents of the shared memory are moved to the buffer while the cache memory is being evaluated.
Since the data is transferred from the buffer to another bus master at the time of a miss hit, the read time from the other bus master is shortened even at the time of a cache memory miss hit.

In the above embodiment, the operation of the system in which the two devices of the CPU 2 and the other bus master 3 share the memory has been described. However, in addition to this, a larger number of processors and various controllers may be used. Even if the memory sharing system is provided with at least one processor having a copy-back cache memory, the same operation is performed and the same effect is obtained. The MI signal and TA signal used in the description of the operation are examples, and other signals can be used.

[0045]

As described in detail above, a CPU provided with a cache memory having a bus snoop function for monitoring access to a shared memory from another bus master and a copy back function for rewriting the shared memory, and these In a system including a CPU and a shared memory shared by other bus masters, when a read request from the other bus master to the shared memory is detected, reading from the other bus master's shared memory is prohibited. At the same time, the contents of the cache memory and the contents that the other bus master tried to execute the read are evaluated, and the contents that the other bus master tried to execute the read are started to be read to the shared memory. If there is a hit, the contents of the shared memory that started reading are transferred to another bus master. Transferred to data, the cache memory is in the case of a hit by transferring the contents of the cache memory to another bus master, the read time from another bus master is shortened even when a miss hit of a cache memory. Therefore, in a memory sharing system having a CPU having a copy-back type cache memory and a memory shared with another bus master, the cache memory of the CPU is It is possible to realize a memory access method and a memory sharing system in which other bus masters can read in a short time even in the case of a mishit.

[Brief description of drawings]

FIG. 1 is a time chart showing a cache miss hit in a memory access method according to an embodiment of the present invention.

FIG. 2 is a time chart showing a cache hit in the memory access method according to the embodiment of the present invention.

FIG. 3 is a configuration diagram showing a configuration of a memory sharing system according to an exemplary embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating a state of memory access according to an embodiment of the present invention.

FIG. 5 is a configuration diagram showing a configuration of a conventional memory sharing system.

FIG. 6 is a time chart showing a procedure of a conventional memory access method.

[Explanation of Codes] 1 bus 2 CPU 2a cache memory 3 other bus master 5 shared memory 6 buffer 7 control circuit

Claims (3)

[Claims] 1. A CPU having a cache memory having a bus snoop function for monitoring access to a shared memory from another bus master and a copy back function for rewriting the shared memory, and a CPU shared by this CPU and another bus master. In a memory access method in a system including a shared memory used as a cache memory, when a read request from another bus master to the shared memory is detected, reading from the shared memory of another bus master is prohibited, and a cache memory When the cache memory misses as a result of the evaluation, the shared memory is started to read the contents that the other bus master tried to execute the read, and the contents that the other bus master tried to execute the read. Reads the contents of the shared memory that started reading Transferred to the master, the memory access method characterized by transferring the contents of the cache memory to another bus master if the cache memory is hit. 2. A cache having a shared memory shared by a CPU and another bus master, a bus snoop function for monitoring access from another bus master to the shared memory, and a copyback function for rewriting the shared memory. When it has a memory and detects a read request from another bus master to the shared memory, it prohibits the read from the other bus master's shared memory and tries to execute the contents of the cache memory and the other bus master. When there is a read request to the shared memory from the CPU that starts the evaluation of the content and another bus master, the shared memory starts to read the content that the other bus master tried to execute, and the CPU evaluates the content. If the cache memory misses after receiving the result of A memory sharing characterized by comprising a control circuit for transferring the contents of the shared memory, which has begun to be read out, to another bus master, and for transferring the contents of the cache memory to another bus master when the cache memory is hit. system. 3. A shared memory shared by a CPU and another bus master, a bus snoop function for monitoring access from another bus master to the shared memory, and a cache having a copyback function for rewriting the shared memory. When it has a memory and detects a read request from another bus master to the shared memory, it prohibits the read from the other bus master's shared memory and tries to execute the contents of the cache memory and the other bus master. A CPU that starts evaluation of the contents, a buffer that temporarily holds the contents read from the shared memory, and another bus master that performs a read when there is a read request from another bus master to the shared memory. The contents to be transferred are transferred from the shared memory to the read buffer, and the CP Control to transfer the contents of the buffer to another bus master if the cache memory has a miss hit in response to the evaluation result from U, and to transfer the contents of the cache memory to another bus master if the cache memory has a hit. A memory sharing system comprising: a circuit.