JPH01118944A - Cache memory controller - Google Patents

Abstract

PURPOSE:To simplify the control logic by always securing the coincidence of contents between a cache memory and a main memory even if a bus master is a CPU or a DMA controller and eliminating the need for the existence of a valid bit of a tag within the cache memory. CONSTITUTION:When a DMA controller 15 serves as a bus master in place of a CPU 11, the controller 15 obtains the necessary data from an input/output device 14 and writes them to a main memory 12 in the next cycle. In this case, the tag memory of a cache memory 13 is checked and the memory 13 is rewritten with new data when an address equal to that of the memory 12 is held by the memory 13. Otherwise no operation is carried out. As a result, the contents of the memory 13 are always coincident with those of the memory 12 even if the bus master is the CPU 11 or the controller 15. Then it is not required to have a valid bit in a tag memory and therefore the control logic is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a cache memory control device suitable for use in a personal computer beater.

(Prior Art) Cage memory is a system used in general-purpose computers, minicomputers, etc. to speed up memory access. These computers generally often employ the path structure shown in FIG. A conventional example will be briefly explained using FIG.

For example, data etc. can be transferred to an input/output device 35 such as a hard disk.
When inputting from 1 Normal DMA controller (DMAC
) j 4 to the main memory 33.

At this time, the CPU 31 is not involved in this operation. Therefore, a mismatch between the contents of the cache memory 32 and the main memory 33 may occur.

(Problem to be Solved by the Invention) In order to deal with the above problem, a valid data pit is prepared in the cache and memory, and when a mismatch occurs, this valid bit is cleared, that is, invalidated, and reading is disabled. Controls are in place to prohibit it. However, these controls are extremely complex, and the control logic is large and expensive.

By the way, recent 32-bit microprocessors are much faster than conventional 8-bit and 16-bit microprocessors, so in order to make the most of their capabilities,
It is possible to use cache memory. etc.
When a cache memory is used in a personal computer, as mentioned above, the logic is complicated and large, which increases the cost.

The present invention has been made in view of this problem, and an object thereof is to provide a cache memory control method that makes the logic simple and small, and further reduces the cost.

[Structure of the Invention (Means for Solving Problems)] The present invention simplifies the cache operation by making the cache memory do not have a valid tag bit, and the CPU and DMA controller become the bus masters to control the bus. In a computer system that uses a main memory and a cache memory that are connected to a path, a data memory that stores a copy of a portion of the data in the main memory, a tag memory that stores tag information, and a voice generated by the device that uses the memory. The controller compares the tag information according to the address that is sent, and the controller becomes the bus master and checks the contents of the tag memory when writing data, regardless of which bus it is. It is equipped with a memory control circuit and a cache which instructs the memory controller to rewrite the data with new data if it has been, and to instruct the memory controller to perform a no-operation if it has not.

(Function) In the above configuration, when the CPU becomes a bus master and becomes a bus, the CPU outputs an address to the address bus and a read status to the control path. At first, the cache and memory operate, and if it is a hit, data is read from the cache and memory but not from the main memory.

If it is a miss, the contents of the cache memory are updated without reading from the cache memory. When the DMA controller becomes the bus master and uses the bus, the DMA controller first obtains necessary data from the input/output device and writes it to the main memory in the next cycle. At this time, the tag memory in the cache memory is checked, and if the same address as the main memory is held in the cache memory, it is rewritten with new data, and if it is not warped, a no-operation is executed.

As a result, the contents of the cache memory always match the main memory regardless of whether the bus is the CPU or the DMA controller when the bus becomes the bus master, and there is no need to have a valid bit in the tag memory, which simplifies control. Furthermore, peripheral hardware can be reduced.

(Example) Examples of the present invention will be described in detail below using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 11 is a CPU that performs overall processing, 12 is a main memory that stores programs and data, and 13 is a CPU.
This is a cache memory for speeding up access to the main memory 33 of No. 11. 14 is an input/output device that exchanges programs and data, and 15 is a next DMA controller (DMAC) that performs DMA transfer between this input/output device 14 and the main memory 12.

Reference numeral 16 denotes a path that commonly connects each of the above-mentioned components 11 to 15. Cage and memory 13 used in the present invention
It is assumed that the direct map method is used and the write control is write-through. The internal configuration of cache memory 13 is shown in FIG.

131 is a tag RAM for storing tag addresses.

132 is a data RAM for storing cached data. 133 stores the tag field of the address bus in the tag RAM when rewriting the tag contents.
A buffer 134 for passing the data to the Z 31 is a controller that determines whether data in the cache memory is hit or not. In addition, 135- is the cash memory 13
This is a control circuit that controls the entire OR@ad/Wrl to.

21 is a tag field in the address bus for determining a hit/miss in the cache memory 13; 22 is an index field in the address bus input as the address of the tag RAM 131 and the data RAM 132; 231rl; 24 is tag data read/written to/from the tag RAM Z 31; 25 is a hit signal output from the comparator 134; 26 is the tag RAM Z 31;
These are signal lines through which control signals for controlling the data RAM 132 and the comparator 134 are propagated.

The operation of the embodiment of the present invention will be explained in detail below. First, when the CPU 11 becomes the bus master and reads from the main memory 12, for example, when reading from the main memory 12, the CPU 11 outputs an address to the address bus and outputs the memory read status to the control path.

First, the cache memory 13 operates, and if it is a hit, data is read from the cache memory 13 but not from the main memory 12. If there is a mistake, the data is stored in the cache memory, and the contents of the cache memory 13 are also updated.

? KK, the case where the DMA controller 15 becomes the bus master and uses the bus will be explained. For example, when reading data from the input/output device 14 and transferring it to the main memory 12, the DMA controller reads the necessary data from the input/output device 14.

At the same time, or DM the read data.
After being held by the A controller 15, it is written to the main memory 12 in the next cycle. At this time, if the cache memory 13 holds the same address as the main memory 12, it is rewritten with new data; otherwise, nothing is done to the cache memory 13. As described above, the contents of the cache memory 13 always match those of the main memory 12, whether the bus is the CPU 11 or the DMA controller 15, which becomes the bus master.

Next, the detailed operation of the cache memory 13 described above will be explained using FIG. 2. There are cases where there are four operations, a combination of read and write, and hits and misses. First, we will only explain when the lead is a hit. When an address is input, the index field 22 is input to the tag RAM 131, where the tag data is output, input to the controller 134, and compared with the tag field 21 of the address previously input. If a match is confirmed here, it is regarded as a hit, and data is output from the data RAM 132 onto the data bus 23. This data is read by a bus such as CPU IZ which becomes a bus master.

Next, I will explain what happens when you make a mistake on the lead. Up to the point where the comparison is made using the combo barre p134, it is the same as when using the lead and the hit described above. They are compared by the comparator 134, and if they do not match, it is considered a miss, the cache memory 13 interrupts its operation, notifies the main memory 12 that there is a miss, and the data from the main memory 12 is output onto the data bus 23. wait for. When data is output, the data is written to the data RAM 132, and furthermore, the tag RAM 1j 1 is written to the buffer 13.
3, the information in the tag field 21 of the address bus is written. Next, I will explain what happens when the light is hit. Similarly, the comparator 134 compares the tags, and if they match, it is considered a hit and the data bus 23
The above data is written to the data RAM 132.

Finally, I will explain what happens when you make a mistake in the right field.

The comparator 134 compares the tags in Mm, and if they do not match, it is considered a miss, and the operation ends without writing to either the tag RAM 131 or the data RAM 132 ◇ As explained above, in the present invention, the cache memory There is a simplification of cache behavior without having tags enabled.

[Effects of the Invention] As explained above, according to the present invention, the DMA controller becomes the bus master, and even if the DMA controller is a bus, there will be no data mismatch between the cache memory and the main memory, and the tags will be valid in the cache memory. There is no need to have a built-in controller, the control logic becomes simpler, and the amount of logic can be reduced. Furthermore, it is possible to reduce costs. As a result of the above effects, a cache memory can be easily incorporated into a personal computer using a high-speed microprocessor at a relatively low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the peripheral portion of the cache memory in FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 11...CPU, 12...Main memory, 13...
・Cache memory, 14... Input/output device, 15
...DMA controller, 131...tag memory, 132...data memory, 133...buffer, 134...con/4'lator, 135...cache memo IJ control circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 3

Claims (1)

[Claims] In a computer system that uses a main memory and a cache memory in which a CPU and a DMA controller are bus masters and are connected to a bus, there is provided a data memory that stores a copy of a portion of the data in the main memory, and a tag memory that stores tag information. , a comparator that compares tag information according to the address generated by the memory-using device mentioned above, and a comparator that checks the contents of the tag memory when writing data regardless of the bus master mentioned above, and maintains the same address in the cache memory as the main memory. 1. A cache memory control device comprising: a cache memory control circuit that rewrites the cache memory with new data if the data has been processed, and instructs the cache memory to perform a no-operation if the data has not been processed.