JPH05233444A - Microprocessor system - Google Patents

Abstract

PURPOSE:To efficiently invalidate only data which are possibly rewritten by other processors in a short period by invalidating data in a specific address range of a cache memory according to the storage contents of a cache control register. CONSTITUTION:When data is written in, for example, a cache control register 111b, a cache invalidation control part 112b is supplied with an invalidation start address and the number of invalidation addresses. The control part 112b invalidates the data in the addresses in the address range on the cache memory 12b to be invalidated with an invalidation control signal. Consequently, data in optional address range on cache memories 12a and 12b can be invalidated by single-time writing operation to cache control registers 111a and 111b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor system, and more particularly to a microprocessor system in which a plurality of microprocessors having cache memories access a common main memory.

[0002]

2. Description of the Related Art In order to improve the performance of microprocessors,
Many methods of incorporating a cache memory are used. This reduces the frequency of access to the main storage device, which is slower than that of the CPU, so that the instruction or data fetched from the main storage device can be accessed again at high speed in the internal cache. This is a technique for improving the performance of the entire system by holding the data in a memory and reading from the high speed cache memory instead of reading from the low speed main storage device when the same address needs to be accessed.

However, when there is a possibility that units other than this microprocessor will use the common main memory device to rewrite the contents of this main memory device, this microprocessor will once take in the cache memory regardless of this rewriting. This behavior may not match the expected behavior of the system as it continues to use the data. An example is shown below.

FIG. 3 shows a configuration example in the case of a microprocessor system in which two microprocessors share one main memory.

1A is a first microprocessor,
A cache memory 12A for data of a direct mapping method of 1 Kbyte and a CPU 11A are provided inside.

1B is a second microprocessor,
This is also the same as the first microprocessor 1A.
The cache memory 12B for K-byte direct mapping data and the CPU 11A are provided.

Reference numeral 2 is a main memory for storing instructions and data, 3 is a 32-bit address bus, and 4 is a 32-bit data bus.

Arbitration circuits and control signals necessary for a microprocessor system in which a plurality of microprocessors access the same bus and main memory are omitted because they are not directly related to the description of the configuration of the present invention.

FIG. 4 shows how the data used by each of the microprocessors 1A and 1B is stored in the main memory 2.

Reference numeral 21a is a 256-byte local work area used by the first microprocessor 1A,
The address from the CPU 11A is “0x0000100
Located between 0 "and" 0x000010FF "(note that 0
The character strings 0 to 9 and A to F starting with x indicate hexadecimal numbers. The same applies below).

Reference numeral 21b is a 256-byte local work area used by the second microprocessor 1B,
The address from the CPU 11B is “0x0000110
It is located between 0 "and" 0x000011FF ".

Reference numeral 22 is a 256-byte common table area commonly used by the first and second microprocessors 1A and 1B. Addresses from the CPUs 11A and 11B are "0x0000FF00" to "0x0000FF".
Located in FF ".

FIG. 5 shows cache memories 12a and 12 built in the first and second microprocessors 1A and 1B.
The data arrangement | positioning state of b is shown.

When the first microprocessor 1A accesses the local work area 21a on the main storage device 2, its copy data is secured in the cache memory 12A. The address of the local work area 21a is "0x00001000" to "0x000010F"
Since it is F ", the address" 0x0 "in the cache memory 12a is associated with the lower 10 bits of this address.
Local work rear 121a from 00 "to" 0x0FF "
The copy data is stored in.

Further, the first microprocessor 1A accesses the common table area 22 on the main memory 2 to secure the copy data in the cache memory 12a. The address of the common table area 22 is “0x0000FF00” to “0x0000FFFF”
Therefore, the address “0x30 in the cache memory 12a is associated with the lower 10 bits of this address.
The copy data is stored in the common table area 122a of "0" to "0x3FF".

Similarly, when the microprocessor 1B accesses the local work area 21b on the main storage device 2, its copy data is secured in the cache memory 12b. The address of the local work area 21b is "0x00001100" to "0x000011F"
Since it is F ", the address" 0x1 "in the cache memory 12b is associated with the lower 10 bits of this address.
Local work area 121 from 00 "to" 0x1FF "
The copy data is stored in b.

The same applies to the common table area 22, and the copy data is secured in the cache memory 12b. The address of the common table area 22 is “0x
Since it is 0000FF00 "to" 0x0000FFFF ", the addresses" 0x300 "to" 0 "in the cache memory 12b are associated with the lower 10 bits of this address.
The copy data is stored in the common table area 122b of x3FF ″.

As described above, since the first and second microprocessors 1A and 1B both access the common table area 22 on the main storage device 2, the copy data thereof are individually stored in the cache memories 12A and 12B. I will have. This common table area 122a,
The copy data of 122b needs to be exactly the same as that in the common table area 22 on the main memory 2, but for example, the first microprocessor 1A rewrites a part of the copy data of the common table area 122a. In this case, the data in the common table area 22 for the main memory 2 is updated from the first microprocessor 1A, but the second microprocessor 1B on the other side is updated.
Does not know that the data in the common table area 22 has been changed, the copy data in the common table area 122b of the cache memory 12b on the second microprocessor 1B remains old, and the main storage device 2 is directly accessed. There is a difference from when you do it.

In order to prevent the occurrence of this problem, when a plurality of units operate a common area such as the common table area 22, the area may not be taken into the cache memory, or it may have been rewritten from another area. In this case, the method of initializing the cache memory is used.

For example, when the first microprocessor 1A switches to the second microprocessor 1B, the second microprocessor 1B may have an old copy in its cache memory 12b. For this reason, first, after switching, one's own cache memory 12b
Invalidates all the copy data stored in. After that, when the data in the common table area 22 becomes necessary, the data is transferred from the main storage device 2 to the cache memory 12 again.
By reading the copy data into b, the data match (cache coherency) between the main memory 2 and the cache memory 12b is always maintained.

For example, in the i486DX microprocessor manufactured by I Corporation of the United States, the INVD instruction (Invalidate
Data Cache) instruction can be used to invalidate the contents of the data cache memory to keep the data in the main memory and the data cache memory consistent (reference: Nikkei Data Pro Microprocessor 1991 No. 11). MC 1-303-389).

Further, in the μPD-0832 microprocessor manufactured by our company, the contents of the data cache memory are invalidated by using the cache control word, which is one of the control registers, so that the cache memory between the main storage device and the data cache memory is invalidated. The data can be kept consistent (reference: Nikkei Data Pro Microprocessor, 1989, No. 5, MC1-304-323).

In this case, however, the entire cache memory must be invalidated in order to discard the common portion, and even the portion that the microprocessor was using locally is also discarded and is rewritten by another unit. There is a waste of having to read the data, which may not exist, from the main storage device 2 again.

There is also a method of invalidating only the portion corresponding to the common area in order to leave local data in the cache memory that does not need to be discarded. For example, MC6 manufactured by US M company
Since the 8020 can invalidate only the data of one address in the cache memory by the designation by the cache address register, by repeating this method while changing the address, the data of only a specific range can be invalidated. (Reference: Nikkei Data Pro
Microprocessor 1989 Issue 3 MC1-303-
(See page 551).

[0025]

In this conventional microprocessor system, either the entire cache memory is invalidated, or only the data of one address in the cache memory is invalidated. Therefore, in the former example, ,
There is a waste of invalidating the data that each microprocessor uses locally and cannot be rewritten by other microprocessors. In the latter example, when invalidating data in a specific address range, However, there is a problem that the processing time becomes long because the addresses are sequentially changed and invalidated one by one.

An object of the present invention is to provide a microprocessor system capable of invalidating only data in a specific address range which may be rewritten by another microprocessor or the like in a short time.

[0027]

SUMMARY OF THE INVENTION A microprocessor system of the present invention includes a main storage device having a common area and a plurality of local areas for storing data, and a common area corresponding to the common area of the main storage device. And a cache area having a local area corresponding to one of the local areas and storing predetermined data stored in the common area and the local area of the main memory, and a specific address range of the cache memory. And a plurality of microprocessors each including a CPU having a cache invalidation control unit that invalidates data in a specific address range of the cache memory at a predetermined timing according to the stored contents of the cache control register. is doing.

[0028]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The main storage device 2 is the same as the conventional example shown in FIGS. 3 and 4. In addition, the microprocessor 1a,
The cache memories 12a and 12b in 1b are also the same as those of the conventional example shown in FIGS.

CPU of the microprocessor 1a (1b)
11a (11b) is the cache memory 12a (12
b) The cache control register 111a (111b) for storing the specific address range, and the data in the specific address range of the cache memory 12a (12b) is invalidated at a predetermined timing according to the stored contents of the cache control register 111a (111b). And a cache invalidation control unit 112a (112b) that activates the cache.

FIG. 2 shows the cache control register 111a,
The internal configuration of 111b, the cache invalidation control units 112a and 112b and the cache memory 12a,
12b and 12b.

Cache control registers 111a, 111
The specific address range of the cache memories 12a and 12b stored in b is the common table areas 122a and 12b.
2b is a predetermined address range, and the predetermined address range is defined as the invalidation start address CSA and the invalidation address number C.
Specified by AN, the cache control register 111
Reference numerals a and 111b denote an invalidation start address field CSAF for storing the invalidation start address CSA and an invalidation address number field CA for storing the invalidation address number CAN.
The configuration includes an NF and an invalidation designation bit CDB that designates invalidation of the cache memory.

Next, the operation of this embodiment will be described.

As described in "Prior Art", when the contents of the common table area 22 in the main memory 2 are rewritten by the first microprocessor 1a, the cache memory 12b of the second microprocessor 1b is rewritten. The contents of a certain common table area 12b and the contents of the common table area 22 on the main memory 2 do not match. Therefore, the common table area 122b in the cache memory 12b is at the stage when the processing of the first microprocessor 1a ends and the processing of the second microprocessor 1b starts.
Invalidate the contents of.

Specifically, for example, the common table area 1
When invalidating the entire contents of 22b, "0x300", which is the start address of the common table area 122b, is set in the invalidation start address field CSAF as "0x300" to "0x3FF". Invalidate address field CA
In the NF, "1" is set to the invalidation designation bit CDB to start the invalidation, and "0x300100" is set.
The data "01" is stored in the cache control register 111b.
Write in.

When a write occurs in the cache control register 111b, the invalidation start address CSA and the invalidation address number CAN are given to the cache invalidation control unit 112b. The cache invalidation control unit 112b invalidates the address range to be invalidated in the cache memory 12b, that is, the data of the addresses "0x300" to "0x3FF" in this example, in response to the invalidation control signal CNE.

As described above, in the embodiment, the invalidation of the data in the arbitrary address range on the cache memories 12a and 12b can be realized by one writing operation to the cache control registers 111a and 111b. Thus, only the data in the address range that may be rewritten can be efficiently invalidated in a short time.

[0039]

As described above, according to the present invention, the cache control register for storing a specific address range of the cache memory in the CPU and the stored contents of the cache control register and accordingly the data of the specific address range of the cache memory are invalid. By providing the cache invalidation control unit for invalidating, the data in the predetermined address range can be invalidated by one address range designation and invalidation operation, so that it may be rewritten by another microprocessor or the like. There is an effect that it is possible to effectively invalidate only the data with a short time in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a cache control register of the embodiment shown in FIG. 1 and a mutual relationship between a cache control register, a cache invalidation control unit, and a cache memory.

FIG. 3 is a block diagram showing an example of a conventional microprocessor system.

FIG. 4 is a storage content layout diagram of a main storage device of the microprocessor system shown in FIG.

5 is a storage content layout diagram of a cache memory of the microprocessor system shown in FIG. 3. FIG.

[Explanation of symbols]

 1a, 1b, 1A, 1B Microprocessor 2 Main memory device 3 Address bus 4 Data bus 11a, 11b, 11A, 11B CPU 12a, 12b Cache memory 21a, 21b Local work area 22 Common table area 111a, 111b Cache control register 112a, 112b Cache invalidation control unit 121a, 121b Local work area 122a, 122b Common table area CANF Invalidation address number field CDB Invalidation designation bit CSAF Invalidation start address field

Claims (2)

[Claims] 1. A main storage device having a common area and a plurality of local areas for storing data in these areas,
A cache memory having a local area corresponding to one of a common area and a local area corresponding to the common area of the main memory, and storing predetermined data stored in the common area and the local area of the main memory in these areas. And a cache control register for storing a specific address range of the cache memory and a cache invalidation control unit for invalidating data in the specific address range of the cache memory at a predetermined timing according to the stored contents of the cache control register. And a plurality of microprocessors each including a CPU. 2. A specific address range of the cache memory is a predetermined address range of the common area, and the predetermined address range is designated by an invalidation start address and the number of invalidation addresses, and the cache control register sets the invalidation range. 2. The microprocessor system according to claim 1, further comprising: an invalidation start address field for storing an invalidation start address, and an invalidation address number field for storing the invalidation address number.