JPH0373040A - Cache memory - Google Patents

Abstract

PURPOSE:To improve efficiency for using a system bus by controlling a write data buffer with n-byte width in a cachememory for each byte and writing the data of n-bytes to a main memory by using the system bus after the data are stored to the write data buffer. CONSTITUTION:At the time of a read access or when a word address is changed, a write buffer control circuit 40 starts a bus request to the main memory and when there is a response from a bus controller, the data of a write data buffer 50 are written into a main storage device 10. The write data buffer 50 is equipped with latch control for each byte and the data of the byte, to which the output of a decoder 3 is inputted, are latched. When the output of the write buffer control circuit 40 is active, an address driver 8 and a data driver 9 output the contents of a write address buffer 7 and the write data buffer 50 through a system bus 801 to the main storage device 10. Thus, the efficiency for using the system bus can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory for an information processing device, and more particularly to write buffer control in a write-through type cache memory.

[Conventional technology]

Referring to FIG. 4, a write-through type cache memory 2 having a conventional write buffer 5 with a data width of n bytes is operated by a latch signal 41 generated from a write control signal 102 from the processor 1. data 1
04 is latched into the write data buffer 5 at a time, and then the data in the write data buffer 5 is written to the main memory 10 using the system bus 801 via the driver 9.8 along with the word address 101 stored in the write address buffer 7. It was.

[Problem to be solved by the invention]

In the above-mentioned conventional cache memory, data is written to the main storage device 10 for each write access from the processor 1, so even when there are successive write accesses to successive addresses as in the case of string processing, 1 novate data is latched into the write buffer 5, and the system bus 801 with a width of n bytes is used each time to write the main message +! 10 to system bus 80
The disadvantage was that the usage efficiency of 1 was poor.

[Means to solve the problem]

The cache memory of the present invention includes an n-byte wide write data buffer that has latch control for each byte, and means (for example, a decoder) for generating a latch signal for each byte of the write data buffer from a byte control signal from the processor side. , in the case of a byte write access, instead of writing to the main memory immediately, the processor detects that the next access is a read access or a write access to a different word (n byte address) and writes the write data buffer at that time. It is characterized by having a write buffer control circuit that writes data to the main memory.

Note that it is preferable that a write address buffer with n-byte addresses is also provided, and that the write address stored therein is also controlled to be sent to the system bus together with the write data.

In the cache memory of the present invention, data storage in the n-byte wide write data buffer is controlled for each byte,
When byte accesses of consecutive addresses occur in sequence, writing from the write data buffer to the main memory using the system bus is not performed until n bytes of data are stored and the write buffer is full. System bus usage efficiency can be increased n times compared to the conventional system.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, showing only the parts related to the present invention. In this example, 32 bits (4 bytes)
We will explain a system with a data width of .

In FIG. 1, a processor 1 has a word address signal 1
01. Read/write control signal 102. A byte address signal 103 and a 32-bit write data signal 104 are output. The cache memory 2 updates the cache memory with write data at the time of write bit. The decoder 3 according to the present invention indicates the byte position indicated by the byte address 103 and outputs corresponding byte control signals 301, 302, 303, and 304. Write buffer control circuit 4
0 is the read/write control signal 102. The output 601 of the address transition detection circuit 6 is input, and in the case of read access or when the word address (4 bytes) changes, a bus request to the main memory is opened, and if there is a response from the bus controller, a driver control signal is sent. 401 and writes the data in the write data buffer 50 to the main memory 10. The write data buffer 50 has latch control for each byte and the output of the decoder 3 is 301°302.30.
3, 304 latches the input byte data.

Address transition detection circuit 6 is a word address (4 bytes)
101 is detected, and a detection signal 601 is output to the write buffer control circuit 40. Write address buffer 7
stores the write address 101. Address driver 8 and data driver 9 output the contents of write address buffer 7 and write data buffer 50 to main memory 10 through system bus 801 when output 401 of write buffer control circuit 40 is active. This will be explained with reference to a timing chart. A processor cycle is a memory cycle in IT. In this example, it is assumed that the word address 101 does not change between T1 and T4, and byte write access is performed under byte control. In this case, of the write data 104, 8-bit data A of Do to D7 is written in the T1 cycle, 8-bit data B of D8 to D15 is written in the T2 cycle, 8-bit data C of D16 to D23 is written in the T3 cycle, and 8-bit data C of D16 to D23 is written in the T4 cycle. Here, it is assumed that the 8-bit data D of D24 to D31 are each valid data. These data A to D are written into each byte of the write data buffer 5o by byte control signals 301 to 304 from the decoder 3, respectively. That is, only bytes whose byte control signal is active are written. Also, the output data 501, 502, 503 of each byte of the write data buffer 50,
504 also changes as shown in the figure in response to writing. Since the word address 101 changes in processor cycle T5, the output signal 601 of the address transition detection circuit 6 becomes active, and the output signal 601 of the write buffer control circuit 40 becomes active.
By 01, the contents of the write buffer, ie A, B, C,
The 4-byte data of D (Do to D3□) is output to the system bus 801.

FIG. 3 is a block diagram of a second embodiment of the invention. This embodiment has two stages of write address buffers and write data buffers (7 and 12, 50 and 11).
This is an example of having In this example, when the preceding write data buffer 50 is full, or in the case of read access or byte write access with different words, the output signal 402 of the write buffer control circuit 40 transfers the contents of the preceding write data buffer 50 to the subsequent write data buffer 11. It's hard to do. Next, when the write data buffer 50 is full or there is a read access or a byte write access with a different word, the write data buffer 1 of the subsequent stage
The contents 11○1 of 1 are output to the system bus 801 and written to the main memory 10.

〔Effect of the invention〕

As explained above, the present invention controls the n-byte wide write data buffer of the cache memory byte by byte, and after n-byte data is stored in the write data buffer, the write data is written to the main memory using the system bus. By performing this, even when byte write accesses such as string processing are continuous, the system bus having an n-byte width can be used n times more efficiently than when accessing each byte at a time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of the first embodiment of the present invention, and FIG.
The figure shows a timing chart of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a block diagram of a conventional example. 111. Processor, 2... Cache memory, 3.
...Decoder, 4.40...Write buffer control circuit, 5.50.11...Write data buffer, 6...
・Address transition detection circuit, 7.12... Write address buffer, 8... Address driver, 9... Data driver, 10... Main memory, 101... Word address signal, 102... Read /light control signal, 1
03... Byte address signal, 104... Write data signal, 301, 302, 303, 304... Byte control signal, 401... Driver enable signal, 5
01.502, 503, 504...Write data buffer 5 output signal, 601...Address transition detection circuit output signal, 801...System bus, 1101...Write data buffer 11 output signal. 4th cycle

Claims (1)

[Claims] A write-through type cache memory with a data width of n bytes includes an n-byte wide write data buffer that can latch control each byte, and a write data buffer that receives a byte control signal from the processor side to write to the write data buffer. means for generating a latch signal, and at least detecting that the next access by the processor is a write access to an address of a word different in n-byte width, and transferring the write data already stored in the write data buffer to the main memory. A cache memory comprising a write buffer control circuit that controls writing.