JPH0816539A - Data transfer method and distributed memory type parallel computer and element processor realizing this method - Google Patents

Abstract

PURPOSE:To provide a data transfer method, where an arbitrary processor can start to transfer data between arbitrary processors without paying the attention to the processor to which data belongs, and the parallel computer and processors which execute this method. CONSTITUTION:A transmission source address register 117 ana a transmission destination address register 118 are prepared in an interface 208, and the global address by which all of the main storage in the parallel computer can be referred to is set to registers 117 and 118 at the time or the start or data transfer, and element processors of the transmission source and the transmission destination are discriminated by set values. A message sending part 103, a message reception part 106, and a header analysis part 107 are provided. If the transmission source is the processor itself, the part 103 starts data transfer; but if it is another processor, the part 103 transmits parameter values for data transfer start to the element processor of the transmission source as a message. The part 106 receives data transferred to the processor itself and starts data transfer in accordance with a message which requests the processor itself to be the transmission source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method in a distributed memory type parallel computer, a distributed memory type parallel computer and an element processor for realizing the same, and in particular, any element processor constituting the parallel computer itself. The present invention relates to a data transfer method capable of transmitting and receiving data between main memory devices included in any two (sending side and receiving side) element processors, a distributed memory parallel computer and an element processor for realizing the method.

[0002]

2. Description of the Related Art In recent high information society, there has been a strong demand for an increase in the processing amount of an information processing device and a high processing speed, and in order to meet the demand, a plurality of arithmetic processors are configured in cooperation with each other. A parallel computer was developed.
A parallel computer has a plurality of arithmetic processors, and the plurality of arithmetic processors are configured to use one memory in common. This kind of parallel computer has TCMP (Ti
ghtly Coupled Multi-Proce
(ssor) type parallel computer. On the other hand, TC
A parallel computer having more arithmetic processors than the MP type, specifically, hundreds to thousands of arithmetic processors has appeared. From the viewpoint of hardware implementation difficulty, this parallel computer has adopted a method in which each arithmetic processor has an independent memory, rather than a method in which all arithmetic processors share one memory. , Is called a distributed memory parallel computer. The distributed memory type parallel computer can achieve higher performance than the TCMP type parallel computer. However, since the distributed memory type parallel computer is provided with the memory distributed among multiple arithmetic processors, portability and ease of programming based on the conventional programming style assuming a single arithmetic processor and a single memory. There was also a point that there was a problem with. Therefore, recently, a distributed shared memory method has been introduced for a distributed memory type parallel computer as typified by research at Stanford University in the United States, which allows each arithmetic processor to refer to the memory of another arithmetic processor. The tendency to do is increasing.

In order to realize the distributed shared memory, there is a problem of how to refer to the memory of another arithmetic processor. This problem is solved by addressing. Specifically, the memory of another arithmetic processor is mapped in its own address space. The address space realized by this is hereinafter referred to as a global address space. FIG. 6 is an example of the global address space. The global address space 601 is divided into the number of element processors constituting a parallel computer. The divided areas 603, 605, ... 607 are allocated to different element processors. .. 606 in each of the areas 603, 605, .. For example, RP3, which is a parallel computer experimentally prototyped by IBM
Then, the 1985 International Co
nference on Parallel Proc
Essing's abstracts, pages 782-789, "RP3 Processor-Memor"
As described in "Y Element" and Japanese Patent Publication No. 5-20776, an address of the form shown in FIG. 13 is used to refer to a memory of another arithmetic processor.
In the address shown in FIG. 13, the arithmetic processor having the memory to be referred to is designated by the processor number field 1301, and the address in the memory is designated by the offset field 1.
It is designated by 302.

[0004]

In the above-mentioned conventional distributed shared memory system, when one arithmetic processor refers to the memory of another arithmetic processor, the same load / load as when referencing the memory of its own processor is used. I used a store command. In other words, if the distributed shared memory system is regarded as a data transfer interface between the element processors constituting the parallel computer, the conventional distributed shared memory implementation system could only realize data transfer of small granularity in word units. For example, considering application of this parallel computer to database processing, when a large-scale (memory-to-memory) copy of a database occurs, a large amount of word-unit data transfer must be performed, resulting in large overhead and performance. Is a big problem. Also, with this interface, the processor itself that activates data transfer must be either the data transfer source or the data transfer destination. That is, this interface is
It is a two-way interface only. On the other hand, the message passing interface that is basically supported by the distributed memory type parallel computer is an interface that can transfer several words to several hundreds or thousands of words at a time. However, in the conventional message passing interface, it is necessary to explicitly specify the processor number of the data transmission destination. Further, the data to be transmitted had to exist in the memory of the own processor. That is, the conventional message passing interface is a one-way interface from the own processor to another processor. The purpose of the present invention is to
A data transfer method that does not consider the processor to which the data group belongs and that targets a variable amount of data and that can activate arbitrary element processors between arbitrary element processors. To provide a computer and an element processor.

[0005]

In order to solve the above problems, the present invention introduces a concept of a global address space realized by a distributed shared memory system into a conventional data transfer system based on a message passing interface. It is a thing. Specifically, as shown in FIG. 5, the start address (src-adr) of the source processor (in this case, the own processor) of the data group to be transmitted, the destination processor number (dst-PU #), the transmission The start address (dst-ad
r), the data transfer amount (length), and the existence interval (strid) of the data to be transmitted / received in the memory area.
The conventional message passing interface expressed mainly by five parameters in e) is changed, and as shown in FIG. 3, the head global address (src-adr) of the data group to be transmitted and the write destination of the transfer data group are changed. An interface represented by four parameters, that is, the leading global address (dst-adr), the data transfer amount (length), and the existence interval (stride) of the data to be transmitted and received in the memory area is defined. This interface is for distributed memory type parallel computers.
An interface for referencing all of the main memory devices belonging to each of the element processors constituting the parallel computer by a global address space and realizing data copy between memory areas from an arbitrary global address area to another arbitrary global address area Is. The present invention is characterized in that data transfer is realized in a copy mode by using such an interface.

[0006]

According to the present invention, data transfer can be realized in the distributed memory type parallel computer by the concept of data copy between memory areas by the above means. Therefore, even when referring to the global address space, a data group of hundreds or thousands of words from a word unit can be targeted at one time. Further, from the viewpoint of data transfer, the data transfer initiator does not need to be aware of the processor to which the data or data group belongs. This feature has the effect of increasing the ease of writing a program for a parallel computer to which the above means is applied. Further, in the data transfer method realized by the above means,
Data can be transferred between arbitrary element processors (between arbitrary main storage devices), and the data transfer initiator is not defined as either a data transfer source or a data transfer destination. That is, the element processor A which is neither the element processor B nor the element processor C can instruct the data transfer from the element processor B to the element processor C. This is a multi-directional interface that surpasses the conventional message passing interface, which was only a one-way interface, and the conventional data transfer interface based on the distributed shared memory method, which was at most bi-directional. It has a great effect of improving the easiness of writing the program. In particular, this feature is considered to have a great effect on the server / client model program description.

[0007]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 shows an embodiment of an element processor constituting a distributed memory type parallel computer. In the figure, an element processor 201 is connected to an instruction processor 202 that executes a program process, an instruction processor 202, and in accordance with a command / address / data set issued from the instruction processor 202, a main storage device 207 and an I / O device described later. 205 and the network interface 208, a memory access interface 203 for issuing access to the inside, an I / O interface 204, a memory control unit 206, other element processors (having the same configuration as 201), and an element processor coupling network (network). ), A network interface 208 for transferring packets and data, an I / O device 205 connected to the I / O interface 204, a main storage device 207 connected to the memory control unit 206, And a bus 209 connecting the memory access interface 203, I / O interface 204, the memory control unit 206 and the network interface 208
Etc. The present invention relates to a network interface 208 that is the basis of a data transfer mechanism that realizes data transfer.

Next, the data transfer interface defined in the present invention will be described. FIG. 3 shows the data transfer interface defined in the present invention in the form of a function using a programming language such as C language. When expressing data transfer in a program suitable for a parallel computer to which the interface is applied, it is actually described in a form according to FIG. The first parameter “src-ad in FIG. 3
r "is the head global address of the series of data to be transferred. Also, the second parameter" dst-adr ".
Is the leading global address of the write destination of the transfer data group. The third parameter “length” is the transfer data amount, and the fourth parameter “stride” is the existence interval of the transfer target data in the memory area. As shown in FIG. 14, "stride" is, for example, 1 when transfer target data that are continuous in the transfer order are adjacent to each other in the address order, and 2 when every other data is in the address order (the same applies hereinafter).

In the data transfer interface defined in the present invention, it is necessary to specify at least three parameters of the first, second and third parameters among the four parameters shown in FIG. 3 (stride is fixed to 1). By doing so, on the contrary, other parameters can be set by expanding this data transfer method). FIG. 3 shows "src-adr".
"Length" starting from the global address
× After reading “length” data from “stride” data areas at “stride” intervals, all the read data are “length” starting from a global address “dst-adr” ×
“Stride” to “stride” data area
It represents an operation of writing only "length" pieces at intervals. That is, what is realized using this interface can be regarded as a data copy between memory areas from an arbitrary global address area to another arbitrary global address area rather than data transfer. It should be noted that what is expressed as a global address in the above is an address in the global address space as illustrated in FIG. 6, and has a format as shown in FIG. 13, for example. In the addresses shown in FIG. 13, an element processor having a memory to be referred to is designated by a processor number field 1301 and an address in the memory is designated by an offset field 1302. The global address space 601 of FIG. 6 is divided into the number of element processors, and the divided areas 603, 605, ... 607.
Are assigned to different element processors. Then, the respective regions 603, 605, ... 6
Areas 602, 604, ... 606 in 07 are mapped with the main memory of the corresponding element processor.

Next, the configuration and operation of each part of the network interface 208 according to the present invention will be described in detail with reference to FIG. In addition, in advance, the signal line L15 of FIG.
L16 and L17 will be described without any misunderstanding. Due to space limitations, each signal line is filled with the image running under or behind the square that represents some registers. The signal line L15 passes under the transmission source address register 117, and the message transmission unit 103
It becomes the input signal of. The signal line L16 is connected to the destination address register 118 and the source address register 11
It is an input signal of the message transmission unit 103 through the bottom of the number 7. The signal line L17 is the transmission data length register 11
9. The message sending unit 103 passes under the destination address register 118 and the source address register 117.
It becomes the input signal of. The connection relationship between the network interface 208, the bus 209, and the network in FIG. 1 is as described above with reference to FIG.

The network interface 208 is roughly composed of four parts, a message sending part, a message receiving part, a main memory access part and a bus interface part 101. The message transmission unit includes a message transmission unit 103, a transmission source address register 117, a transmission destination address register 118, and a transmission data length register 11.
9, a transmission stride width register 120, a write control unit 121, a selector 123, a selector 124, a request arbitration unit 122 that arbitrates a request from the own processor and a data transfer request (from the header analysis unit) via the network,
The address addition unit 116, the comparator 104, the own PU number register 105 (PU is an abbreviation for element processor), and the like. The message receiving unit is composed of a message receiving unit 106, a header analyzing unit 107, an address adding unit 112 and the like. The main memory access unit is the main memory reading unit 12
5 and a main memory writing unit 128. The bus interface unit 101 is connected to the bus 209, receives the following three types of requests transmitted from the instruction processor 202 via the memory access interface 203, and further via the bus 209, and performs necessary processing. (1) Transmission of the message transmission start command signal L1 to the message transmission unit 103. (2) Message transmission request signal L to the request arbitration unit 122
13 transmissions. (3) Writing values to the source address register 117, the destination address register 118, the transmission data length register 119, and the transmission stride width register 120. Further, the bus interface unit 101 includes the request arbitration unit 1
Inversely, the arbitration result of 22 is passed through the memory access interface 203 via the bus 209, and the instruction processor 20
Tell 2. In addition, the bus interface unit 101 is a main memory reading unit 1 in the network interface 208.
25 and main memory access from the main memory writing unit 128 are realized.

A source address register 117, a destination address register 118, a transmission data length register 119, and a transmission stride width register 120 in the message transmission unit.
Are the four parameters “s” shown in FIG. 3, respectively.
"rc-adr", that is, the head global address of a series of data to be transferred, "dst-adr", that is, the head global address of the write destination of the transfer data group, "l"
"length", that is, the transfer data amount, "stride"
That is, it is a register for storing the existence interval of the transfer target data in the memory area. In the source address register 117 and the destination address register 118,
Since the global address having the format illustrated in FIG. 13 is stored, the register 701 shown in FIG. 7 is used. The register 701 has a processor number field 1301 and an offset field 13 in FIG.
PU number field 7 to store each 02
02 and PU address field 703.

From the message transmission unit, two types of message transmission, request message transmission and data message transmission, can occur depending on the contents of the source address register 117. If the value of the signal line L25 that conveys the contents of the PU number field of the source address register 117 and the value of its own PU number register 105 are compared by the comparator 104 and the values are equal, data message transmission occurs. On the contrary, if the comparison result in the comparator 104 indicates that the values are different, a request message transmission requesting data transfer is generated to the element processor indicated by the contents of the PU number field of the transmission source address register 117. Separate message headers 901 and 1001 shown in FIGS. 9 and 10 are defined for the request message and the data message, respectively.

The message header 901 of FIG. 9 for the request message includes a message type 902 and a source PU.
Number 903, source address 904, destination address 9
05, transmission data length 906, transmission stride width 907, and the like. The message type 902 is information (possible with 1 bit) indicating a request message / data message, and in this case, indicates a request message. The source PU number 903 is the source address register 1 transmitted to the message sending unit 103 via the signal line L14.
It is the contents of the PU number field of 17, that is, the number of the element processor having the main storage device in which the data to be transferred is stored. The source PU number 903 is
It is also the number of the destination element processor of this request message itself. Source address 904, destination address 90
5, the transmission data length 906, the transmission stride width 907,
A source address register 117, a destination address register 118, a transmission data length register 119, and a transmission stride width register 1 which are transmitted to the message transmission unit 103 via the signal lines L14, L15, L16, and L17, respectively.
These are the contents of 20.

The message header 1001 of FIG. 10 for the data message includes information such as the message type 902, the destination PU number 1003, the destination address 905, the transmission data length 906, and the transmission stride width 907. The message type 902 is information indicating the distinction between request message / data message as described above,
In this case, a data message is shown. Destination PU number 10
03 is the message sending unit 103 via the signal line L15.
It is the contents of the PU number field of the destination address register 118 transmitted to the device, that is, the number of the element processor having the main memory to which the data to be transferred is written. The destination PU number 1003 is also the number of the destination element processor of this data message itself. The transmission destination address 905, the transmission data length 906, and the transmission stride width 907 are signal lines L15, L16, and L17, respectively.
Destination address register 118, transmission data length register 119, which is transmitted to the message sending unit 103 via
It is the content of the transmission stride width register 120.

The message sending unit 103 is based on the information transmitted via the signal lines L14, L15, L16 and L17 according to the comparison result of the comparator 104 transmitted via the signal line L8, and is as described above. The message headers for the request message and the data message are separately created, and the message header is sent to the network through the signal line L4 to classify the request message and the data message. Further, if the transmission is a data message transmission, the transfer data is transmitted after the message header is transmitted. The data message packet is shown in FIG. The transmission of the transfer data is realized by the message transmission unit 103 transmitting a main memory read request to the main memory read unit 125 via the signal line L6. The main memory reading unit 125 is the bus interface unit 1.
The main memory is read via 01, and the read data is sequentially transferred to the message sending unit 103 via the signal line L36. When transferring to the message sending unit 103, a valid signal is also transferred using the signal line L7. In addition,
The valid signal means a signal line L in the machine cycle.
This is a signal indicating that valid read data is on the top. The message sending unit 103 sequentially sends the read data to the network via the signal line L4. The number of transmitted data is counted by the message transmission unit 103, and if the count value becomes equal to the transmission data length transmitted via the signal line L16, the transmission of the transfer data is completed, and with this, the message transmission is completed. On the other hand, when the sent message header is for the request message, the message sending is completed as soon as the sending of the message header is completed.

In order for the message sending unit 103 to start the above operation, it is necessary to send a message sending start signal via the signal line L3. Signal line L
3 is an OR signal of the signal line L1 and the signal line L2. As described above, the signal line L1 is a signal line through which the true value is transmitted as a result of the instruction processor 202 requesting the start of message transmission, and the signal line L2 is requested by the header analysis unit 107 in the message receiving unit to start message transmission. It is a signal line that conveys the true value. When the message sending unit 103 completes sending the message, the message sending unit 103 sends the status to the request arbitration unit 122 via the signal line L41. Instruction processor 20
In order for 2 and the header analysis unit 107 to request the start of message transmission, each must first send a message transmission request to the request arbitration unit 122. The request of the instruction processor 202 is transmitted through the signal line L13 as described above, and the request of the header analysis unit 107 is transmitted through the signal line L11. The request arbitration unit 122 receives these requests and performs priority control in some form, and then sends a signal to the signal line L12 indicating the side that accepts the request when the message transmission is completed. Let The instruction processor 202 and the header analysis unit 107, which have seen the contents of the signal line L12, request the above-mentioned message transmission start if the contents indicate itself.

Since the message transmission unit performs two types of message transmission, that is, a request message transmission and a data message transmission, two types of messages can arrive at the message reception unit 106 of the message reception unit. Generally speaking, when a request message arrives, the message receiving unit requests the message transmitting unit in the same network interface 208 to start the requested data transfer. Also, if a data message arrives,
The main memory writing unit 128 is requested to write the transfer data to the main memory. When a message arrives, the message receiver 106 will send the message type 90 in the message header, which is the first information the message conveys.
The type of message is determined by 2. If the message type is a request message, the message type 902 in the message header 901 and the source address 9
04, the transmission destination address 905, the transmission data length 906, and the transmission stride width 907 are stored in the header register 108 in the header analysis unit 107 via the signal line L9, and the message reception is completed. On the other hand, if the message type is a data message, the message header 1
Message type 902 in 001, destination address 90
5, the transmission data length 906, and the transmission stride width 907 are stored in the header register 108 in the header analysis unit 107 via the signal line L9, and the subsequent transfer data is further stored in the main memory writing unit via the signal line L10. Tell 128.

When the message type is a data message, the header analysis unit 107 determines the header register 108.
The transmission destination address and the transmission stride width in the address addition unit 11 via the signal lines L31 and L32, respectively.
2, and the transmission data length is transmitted as an initial value to the counter 129 in the main memory writing unit 128 via the signal line L35. Further, the main memory writing unit 128 is requested to write to the main memory via the signal line L33. The main memory writing unit 128 that has received the request is the address adding unit 112.
Is transmitted via the signal line L34 and the data transmitted from the message receiving unit 106 via the signal line L10 and set in the register 130 in the main memory writing unit 128 to access the main memory. Repeat the number of times given as an initial value to the counter 129. The message receiving unit 106 receives all the transfer data of the transmission data length, and the register 13 in the main memory writing unit 128 receives it.
When the last data is written to 0, the message receiving unit 106 completes the message reception, and the message receiving unit 106 and the header analysis unit 107 complete the process for the received data message.

On the other hand, when the message type is the request message, the header analysis unit 107 transmits the message transmission request to the request arbitration unit 122 using the signal line L11 as described above, and the request arbitration unit 122 after that. From the signal line L12. When the message transmission request is recognized, the header analysis unit 107 sequentially selects the transmission source address register 117, the transmission destination address register 118, the transmission data length register 119, and the transmission stride width register 120, and selects each register. The signal is sequentially transmitted to the selector 123 via the signal line L22, the value to be written in each register is selected from the corresponding area of the header register 108 each time, and the value is sequentially transmitted to the selector 124 via the signal line L24. Source address register 117, destination address register 118, transmission data length register 11
9 and setting of values in all the registers of the transmission stride width register 120 are completed, the header analysis unit 107
Transmits a message transmission start signal to the message transmission unit 103 via the signal line L2 to start message transmission. The header analysis unit 107 completes the process for the received request message at the time when the message transmission start signal is transmitted to the message transmission unit 103.

The processing request to the message transmission unit in the network interface 208 is performed by the following procedure as described in the processing procedure of the header analysis unit 107 for the received request message. (1) Message transmission request transmission to the request arbitration unit 122. (2) Message transmission approval from the request arbitration unit 122. (3) Setting of parameter values related to message transmission to the transmission source address register 117, the transmission destination address register 118, the transmission data length register 119, and the transmission stride width register 120. (4) Transmission of a message transmission start signal to the message transmission unit 103. The subject that requests the message transmission unit to perform processing is the instruction processor 202 and the header analysis unit 107. All the operations related to the processing request of the header analysis unit 107 are as described above, and the operations related to the processing request of the instruction processor 202 are also (1), (2), (4).
I have already mentioned. The operation (3) of the instruction processor 202 is basically the same as the operation of the header analysis unit 107, and a register selection signal designating a register is
The values to be sequentially transmitted to the selector 123 via the signal line L21 (finally through the access path already described) and written to the respective registers are sequentially signal line L2.
Notify the selector 124 at 3. The instruction processor 2
In response to the processing request from 02, two types of request message transmission and data message transmission can be issued as a result, but with respect to the processing request from the header analysis unit 107,
As a result, only data message transmission can be issued.

Writing of values to the source address register 117, the destination address register 118, the transmission data length register 119 and the transmission stride width register 120 is realized by using the write control unit 121, the selector 123 and the selector 124. The selector 123 and the selector 124 function as a set, and the selector 123 functions as the source address register 117 and the destination address register 11
8, a register designating signal designating any one of the transmission data length register 119 and the transmission stride width register 120 is transmitted to the write control unit 121 via the signal line L19, and the selector 124 writes it in the register designated by the signal line L19. The power value is transmitted to the write control unit 121 via the signal line L20. The value of the signal line L19 is
21 and the signal line L22, and the value of the signal line L20 is either the signal line L23 or the signal line L24. Which to select depends on the signal line L
It is determined by the value of 12, that is, which of the instruction processor 202 and the header analysis unit 107 the request arbitration unit 122 has approved for message transmission.
When the request arbitration unit 122 has approved the message transmission to the instruction processor 202, the value of the signal line L21 and the value of the signal line L23 become the value of the signal line L19 and the value of the signal line L20, respectively. When the request arbitration unit 122 has approved the message transmission to the header analysis unit 107, the value of the signal line L22 and the value of the signal line L24 become the value of the signal line L19 and the value of the signal line L20, respectively. The write control unit 121, based on the register designation signal transmitted via the signal line L19, the source address register 117, the destination address register 118, the transmission data length register 1
19 or the transmission stride width register 120 is selected, and the write paths L18a, L18b, L provided corresponding to the respective registers in response to the selection.
Either 18c or L18d is validated, and the write value transmitted via the signal line L20 is placed on the validated write path. As a result, the value of the signal line L20 is written in the register designated by the value of the signal line L19.

Next, the operation of the main memory access unit outlined above will be described in more detail. Main memory reading unit 12
5 is a message sending unit 10 when sending a data message
3 is activated by an activation signal (main memory read request) transmitted via the signal line L6. The main memory reading unit 125 has a counter 126 and a data register 127 inside. In the counter 126, the value stored in the transmission data length register 119 at that time, which is transmitted via the signal line L26 when the main memory reading unit 125 is activated, is set as an initial value. After that, every time the main memory reading unit 125 issues a main memory reading request, the value of the counter 126 is 1
It is reduced by one. After being activated, the main memory reading unit 125 repeatedly issues the main memory reading request until the value of the counter 126 becomes zero. When the value of the counter 126 becomes 0, the issuance of the main memory read request for sending the data message is completed. When issuing the main memory read request,
The main memory read unit 125 transmits a read command to the main memory access command line L37, and at the same time transmits a read address on the main memory read address line L28. In addition,
The main memory read address line L28 is used as the address adder 116.
It is a signal transmitted from.

The address adder 116 has an adder 1 inside.
15, a selector 114, and an address register 113. The adder 115 adds a value of ((value of transmission stride width register transmitted via signal line L27) × (byte size of transmission unit data)) to the value of the address register 113 and adds the result to the signal line. Output to L29. The selector 114 determines the value of the signal line L29 and the value of the signal line L1.
4 is selected from the values in the source address register 117 transmitted via the address 4, and the selected value is used as the address register 1
Set to 13. However, if the selector 114 is the signal line L
The value of 14 is selected only when the main memory read start signal is transmitted through the signal line L6. In other cases, the value of the signal line L29 is selected. As a result, the address adder 116 that supplies the value of the address register 113 as the main memory read address via the signal line L28.
Supplies the start address of the transfer source data area related to the data message transmission at that time when the main memory reading is started,
After that, it is possible to supply a value that reflects the stride. The read data from the main storage device transmitted via the main storage read data line L38 is sequentially received by the data register 127 and transmitted to the message sending unit 103 via the signal line L36.

On the other hand, the main memory writing section 128 receives the data message from the header analyzing section 107 and outputs the signal line L3.
It is activated by an activation signal (main memory write request) transmitted via the control unit 3. The main memory writing unit 128 has a counter 129 and a data register 130 inside. In the counter 129, the transmission data length value transmitted from the corresponding area of the header register 108 in the header analysis unit 107 via the signal line L35 when the main memory writing unit 128 is activated is set as an initial value. After that, the main memory writing unit 1
Each time 28 issues a main memory write request, the counter 12
The value of 9 is decremented by 1. Main memory writing unit 128
After the activation, the issuance of the main memory write request is repeated until the value of the counter 129 becomes 0. When the value of the counter 129 becomes 0, the main memory writing related to the reception of the data message is completed. At the time of issuing the main memory write request, the main memory write unit 128 transmits the write command to the main memory access command line L39, at the same time transmits the write address on the main memory read address line L34, and the main memory write data line L40. The value of the data register 130 that has been set is transmitted from the message receiving unit 106 via the signal line L10. In addition,
The main memory read address line L34 is connected to the address adder 112.
It is a signal transmitted from.

The address adder 112, like the address adder 116, internally has an adder 111 and a selector 11.
0, address register 109. The adder adds the value of the address register 109 to ((transmission stride width value transmitted from the corresponding area of the header register 108 in the header analysis unit 107 via the signal line L32) × (byte size of transmission unit data)) Is added and the result is output to the signal line L30. The selector 110 uses the signal line L3
Either the value of 0 or the destination (write destination) address value transmitted from the corresponding area of the header register 108 in the header analysis unit 107 via the signal line L31 is selected, and that value is set in the address register 109. . However, the selector 110 selects the value of the signal line L31 only when the main memory write activation signal is transmitted through the signal line L33. In other cases, the value of the signal line L30 is selected. As a result, the address adder 112 that supplies the value of the address register 109 as the main memory write address via the signal line L34 is transferred to the transfer destination (write destination) data area related to the reception of the data message at the time of starting the main memory write. It is possible to supply the start address of the, and thereafter supply a value in which the stride is reflected in the value.

This completes the description of the configuration and operation of each part of the network interface 208 according to the present invention shown in FIG. Next, a flow of data transfer processing based on the data transfer method according to the present invention will be described. The data transfer request is issued from the instruction processor 202. The instruction processor 202 uses the network interface 208.
A request for data transfer is issued to the request arbitration unit 122 inside, and the request arbitration unit 122 waits for permission. At this time, the request arbitration unit 122 includes the same network interface 20.
The data message sending request may arrive from the message receiving section in 8 (specifically, the header analyzing section 107). In that case, the permission is given to the message receiving section as a result of the priority control. In some cases. Instruction processor 2
When the request 02 receives the permission from the request arbitration unit 122, the data transfer parameter “src-adr”, that is, the leading global address of the series of data groups to be transferred, “dst-adr”, that is, the write of the transfer data group The leading global address, “length”, that is, the amount of transfer data, and “stride”, that is, the existence interval of the data to be transferred in the memory area, are sequentially arranged in order of the source address register 117, the destination address register 118, the transmission data length register 119, and the transmission The stride width register 120 is set. When the setting of this parameter is completed, a data transfer start signal is transmitted to the message sending unit 103. This starts the data transfer, and the role of the instruction processor 202 related to the data transfer ends.

Regarding the data transfer started from the instruction processor 202, the parameter "src-adr" set in the source address register 117, that is, the PU of the head global address of the series of data to be transferred.
When the number field value is the own processor number, the main memory reading unit 125 is under the control of the message sending unit 103.
Reads data from its own main storage device 207, and transmission of a data message starts. That is, the data transfer actually starts. This data message is sent to the element processor 201 indicated by the parameter "dst-adr" set in the destination address register 118, that is, the PU number field value of the write destination top global address of the transfer data group. The element processor 201, which is the destination of the data message, receives the message receiving unit 1 in the network interface 208.
When the message is received in 06 and the data message is recognized, the main memory writing unit 128 writes the data received in the main memory device 207 under the control of the message receiving unit 106 and the header analysis unit 107. This data transfer is completed when the writing of all data is completed.

On the other hand, regarding the data transfer started from the instruction processor 202, the source address register 117
If the PU number field value of the parameter "src-adr" set in, that is, the head global address of the series of data to be transferred is not its own processor number, the element processor 2 indicated by the PU number field value
The message sending unit 103 sends a request message to 01. The element processor 201, which is the destination of the request message, receives the message at the message receiving unit 106 in the network interface 208, and when it recognizes that it is the request message, the header analysis unit 107.
Issues a data message transmission request. The header analysis unit 107 issues a data message transmission request to the request arbitration unit 122 in the network interface 208, and waits for permission from the request arbitration unit 122. At this time, the request arbitration unit 122 may receive a data transfer request from the instruction processor 202 in the same element processor 201. In that case, the instruction processor 202 may be permitted as a result of priority control. is there.

The header analysis unit 107 includes a request arbitration unit 122.
When the permission from is obtained, the transmission source address 904, the transmission destination address 905 stored in the header register 108,
Each information of the transmission data length 906 and the transmission stride width 907 is sequentially transmitted to the transmission source address register 117, the transmission destination address register 118, and the transmission data length register 11.
9 and the transmit stride width register 120. When this setting is completed, a data message transmission start signal is transmitted to the message transmission unit 103. This time,
The PU number field value of the global address set in the source address register 117 is always the own processor number. Therefore, this starts the data message transmission. After that, under the control of the message sending unit 103, the main memory reading unit 125 causes the main memory device 20 to
Data is read from 7 and a data message is sent. This data message is sent to the element processor 201 indicated by the PU number field value of the global address set in the destination address register 118. The element processor 201, which is the destination of this data message, uses the network interface 20.
8 receives the message and recognizes that the message is a data message, the data received by the main memory writing unit 128 is controlled by the message receiving unit 106 and the header analyzing unit 107. Write in 207. This data transfer is completed when the writing of all data is completed. The above is the embodiment according to the present invention. In addition, the following can be considered as a modification of the present embodiment.

(Modification 1) The data transfer interface shown in FIG. 3 is modified into an interface as shown in FIG. "Src-adr" and "dst-ad" in FIG.
r ″ is not a global address, but is the address of the main memory device owned by the source element processor 201 and the address of the main memory device owned by the destination element processor 201, respectively. In the interface shown in FIG. Instead of setting “src-adr” and “dst-adr” as global addresses, new parameters “src-PU #” and “dst-PU #” for clearly indicating the source and destination of data transfer are added. Define the remaining "length" and "stride"
Is the same as that of FIG. When the interface shown in FIG. 4 is used, the characteristic that the element processors involved in the data transfer of the interface shown in FIG. 3 need not be considered, but the data transfer between arbitrary element processors (between main storage devices) is arbitrary. It retains the feature that element processors can be started.

The main mechanical changes from the embodiment when the interface shown in FIG. 4 is adopted are the following two points. (1) The source address register 117 and the destination address register 118 having the configuration shown in FIG. 7 have the configuration shown in FIG. 8, and the PU number register 801 and the PU address register 802 are used in combination. If connected and used, the PU number register 801 is used as the PU number field 702, and the PU address register 802 is further used.
As a PU address field 703
1 can be realized in a pseudo manner. (2) The message headers shown in FIGS. 9 and 10 are changed as shown in FIGS. 11 and 12, respectively. More specifically, the source address 904 of FIG. 9 is replaced with the source PU internal address 1104 of FIG. 11, and the destination address 905 of FIG. 9 is the destination PU number 1105 and destination PU internal address 1106 of FIG. 11. replace. Further, the transmission destination address 905 in FIG. 10 is the transmission destination PU address 1 in FIG.
Replaces 205.

(Modification 2) Memory access interface 203 and network interface 2 by bus 209
08 is stopped, and the memory access interface 203 and the network interface 208 are directly connected. At this time, a new interface processing unit is required in the network interface 208 instead of the bus interface unit 101.

[0034]

According to the present invention, in a distributed memory type parallel computer, a program realized by a distributed shared memory system, "a data transfer initiator does not need to be specially aware of a processor to which data or a group of data belongs" While inheriting the high level of ease of description, it has become possible to collectively transfer data groups of hundreds or thousands of words, which could not be realized by the data transfer method realized on the distributed shared memory method. Further, according to the present invention, it is possible to transfer data between arbitrary element processors (between arbitrary main storage devices), and the data transfer initiator is not defined as either a data transfer source or a data transfer destination. That is, the element processor A which is neither the element processor B nor the element processor C can instruct the data transfer from the element processor B to the element processor C. This is a traditional message passing
It is a multidirectional interface that surpasses the interface and the data transfer interface realized on the conventional distributed shared memory system, which is bidirectional at most, and this feature further improves the program description easiness.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a network interface that is a core of a distributed memory parallel computer that implements a data transfer method according to an embodiment.

FIG. 2 is a diagram illustrating a configuration example of an element processor that constitutes a parallel computer according to an embodiment.

FIG. 3 is a diagram showing a data transfer interface in the embodiment.

FIG. 4 is a diagram showing a data transfer interface according to a first modification.

FIG. 5 is a diagram showing a conventional message passing interface.

FIG. 6 is a diagram illustrating a global address space according to an embodiment.

FIG. 7 is a diagram showing a register for storing a global address in the embodiment.

FIG. 8 is a diagram showing a register group that stores a set of values for expressing an arbitrary main storage address in the parallel computer in the first modification.

FIG. 9 is a diagram showing a request message header in the embodiment.

FIG. 10 is a diagram showing a data message header in the embodiment.

FIG. 11 is a diagram showing a request message header in Modification 1.

FIG. 12 is a diagram showing a data message header in Modification 1.

FIG. 13 is a diagram illustrating a format of a global address in the embodiment.

FIG. 14 is a diagram for explaining stride values at the time of data transfer in the embodiment.

FIG. 15 is a diagram showing a data packet in the example.

[Explanation of symbols]

 109 address register 113 address register 127 data register 130 data register 209 bus 701 global address register 801 PU number register 802 PU address register 901 request message header 1001 data message header 1101 request message header 1201 data message header 1301 processor number Field 1302 Offset field

Claims (13)

[Claims] 1. A global address which has a plurality of element processors each having a main memory and a network connecting the plurality of element processors and which can refer to the main memory included in the plurality of element processors. A data transfer method in a distributed memory parallel computer for performing data transfer between element processors by defining and setting a transfer source global address and a transfer destination global address of transfer data from an arbitrary element processor. The processor extracts from the transfer source global address a component indicating a processor number that specifies one of the element processors that form the parallel computer, and sets it as a processor number that specifies the transfer source element processor. The processor number that specifies No., the component indicating the processor number designating one of the element processors constituting the parallel computer is extracted from the transfer destination global address as the transfer destination element processor number, and the transfer destination element A normal data transfer for transferring the data read from the main storage device included in itself to the element processor specified by the processor number specifying the processor using the transfer source global address is performed, and the element of the transfer source When the processor number designating the processor does not match its own processor number, various parameter values set at the time of data transfer are transferred to the element processor designated by the processor number designating the transfer source element processor. A distributed memory type parallel characterized by transmitting as a data transfer request message to Data transfer method in a row computer. 2. The data transfer method according to claim 1, wherein when the normal data transfer and the data transfer request message are transmitted, a message header is created in accordance with necessary information for each of the normal data transfer and the data transfer request. A data transfer method characterized in that the message header is transmitted prior to transmission of the request message. 3. The data transfer method according to claim 1, wherein the message receiving unit in the element processor is
When the normal data transfer is received, the transfer data is written in its own main storage device by using the transfer destination global address of the transfer data, and when the data transfer request message is received, the data transfer request is sent. A data transfer method characterized in that a data transfer request according to the content of a message is issued to itself. 4. The data transfer method according to claim 3, wherein the requests of the instruction processor and the message receiving unit in the element processor as candidates that may request data transfer are arbitrated and arbitrated. A data transfer method characterized in that the data transfer is realized by. 5. A processor number which has a plurality of element processors each having a main memory and a network connecting the plurality of element processors, and which specifies one of the element processors from an arbitrary element processor and the processor number. A data transfer method in a distributed memory parallel computer for performing data transfer between element processors by setting a transfer source and a transfer destination of transfer data with a set value of an address of a main storage device included in an element processor designated by a processor number. When the processor number of the set value specified as the transfer source matches its own processor number, each element processor specifies the processor number of the set value specified as the transfer destination. The main storage device of the set values set as the transfer source of the transfer data toward the element processor. The normal data transfer for transferring the data read from the main storage device possessed by itself is performed using the address of, and the processor number of the set value set as the transfer source of the transfer data is equal to the own processor number. If not done, various parameter values set at the time of data transfer are sent as a data transfer request message to the element processor designated by the processor number of the set value set as the transfer source of the transfer data. A data transfer method characterized by transmitting. 6. The data transfer method according to claim 5, wherein when the normal data transfer and the data transfer request message are transmitted, a message header corresponding to information required for each is created, and the normal data transfer and the data transfer are performed. A data transfer method characterized in that the message header is transmitted prior to transmission of the request message. 7. The data transfer method according to claim 5, wherein the message receiving unit in the element processor is:
When the normal data transfer is received, the transfer data is written in its own main storage device using the address of the main storage device of the set value set as the transfer destination of the transfer data, and the data transfer request is issued. If you receive a message,
A data transfer method, wherein a data transfer request according to the content of the data transfer request message is issued to itself. 8. The data transfer method according to claim 7, wherein the request of each of the instruction processor and the message receiving unit in the element processor as a candidate having a possibility of requesting data transfer is arbitrated, and the arbitration order is arbitrated. A data transfer method characterized in that the data transfer is realized by. 9. A global defined for a main memory device having a plurality of element processors each having a main memory device and a network connecting the plurality of element processors, A distributed memory parallel computer for performing data transfer between element processors by setting a transfer source global address and a transfer destination global address of transfer data from an arbitrary element processor according to an address, wherein each of the element processors comprises: Means for designating a transfer source address and a transfer destination address of transfer data by a global address defined for a main memory device provided in a plurality of element processors constituting a distributed memory parallel computer, and the designated transfer source Elements that make up the above parallel computer from the global address of Transfer source element processor identifying means for identifying a processor number designating a transfer source element processor by extracting a component indicating a processor number designating one of the processors, and the parallel computer from the designated transfer destination global address. And a transfer source element processor identifying means that extracts a component indicating a processor number that specifies one of the element processors that configure the element and identifies a processor number that specifies a transfer destination element processor, and the transfer source element processor identifying means. Comparing means for comparing the processor number with the own processor number, and as a result of the comparison by the comparing means, if the processor number extracted by the transfer source element processor identifying means matches the own processor number, the transfer destination The element processor specified by the processor number extracted by the element processor identification means A normal data transfer for transferring the data read from the main storage device of its own using the transfer source global address, and the processor number extracted by the transfer source element processor identification means and its own processor number are When they do not match, a data transfer request message for transmitting various parameter values set at the time of data transfer to the element processor designated by the processor number extracted by the transfer source element processor identification means as a data transfer request message. A distributed memory type parallel computer, comprising: a data transfer means for transmitting. 10. A processor number which has a plurality of element processors each having a main memory and a network connecting the plurality of element processors, and which specifies one of the element processors from any element processor and the processor number. A distributed memory parallel computer for performing data transfer between element processors by setting a transfer source and a transfer destination of transfer data with a set value of an address of a main storage device included in an element processor designated by a processor number, Each element processor is a transfer source of transfer data with a set value of a processor number designating one of the element processors constituting the distributed memory parallel computer and an address of a main storage device provided in the element processor designated by the processor number. And a means for designating the transfer destination, and a processor of the set values designated as the transfer source. Means for comparing the processor number with its own processor number, and as a result of the comparison by the comparing means, if the processor number of the set value designated as the transfer source and its own processor number match, the transfer destination is determined as the transfer destination. From the main storage device owned by itself using the address of the main storage device of the set value set as the transfer source of the transfer data toward the element processor designated by the processor number of the specified set value When the normal data transfer for transferring the read data is performed and the processor number of the set value set as the transfer source of the transfer data does not match its own processor number, it is set at the time of data transfer. Data of various parameter values is sent to the element processor designated by the processor number of the set value set as the transfer source of the transfer data. A distributed memory parallel computer, comprising: a data transfer means for transmitting as a transfer request message. 11. A main processor having a plurality of element processors and a network connecting the plurality of element processors, each element processor constituting a different part of a main memory shared by the element processors. In a distributed memory type parallel computer having a memory for storage, a first element of a data transfer request designating a transfer source address and a transfer destination address described by a global address defined for the main storage device Issued by the processor, the first element processor sends the transfer request to the second element processor having the main storage memory to which the transfer destination address belongs, and the main storage memory in the second element processor The transfer data from the storage location having the transfer source address included in the transmitted transfer request in Then, the read data is transferred together with the transfer destination address to a third element processor having a memory for main memory to which the transfer destination address included in the transfer request belongs, and the main memory of the third element processor Data transfer method for writing the transferred data to a storage location having the transferred transfer destination address in the memory for use. 12. A plurality of element processors and a network connecting the plurality of element processors, each element processor serving as one of a plurality of parts of a main memory shared by the element processors. A main memory to be used, a circuit for issuing a data transfer request designating a transfer source address and a transfer destination address described by a global address defined for the main memory, and a circuit for responding to the transfer request. A circuit for transmitting the transfer request from each of the element processors to any of the element processors having the main memory to which the transfer destination address belongs, and in response to the transfer request transmitted from any of the processors, A circuit for reading transfer data from a storage location having the transfer source address included in the transmitted transfer request; A circuit for transmitting the read data together with the transfer destination address to any one of the element processors having a memory for main memory to which the transfer destination address included in the received transfer request belongs; A circuit for writing the transferred data to a storage location having the transferred transfer destination address in the main memory of each element processor in response to the transferred transfer destination address and the data. Memory type parallel computer. 13. A main processor comprising a plurality of element processors and a network connecting the plurality of element processors, each element processor constituting a different part of a main memory shared by the element processors. An element processor for a distributed memory type parallel computer having a memory for storage, which is defined for a memory for main memory to be used as one of a plurality of parts of a main memory shared by the respective element processors. Circuit for issuing a data transfer request designating a transfer source address and a transfer destination address described by a global address, and a main memory for which the transfer destination address belongs from each element processor in response to the transfer request. A circuit for transmitting the transfer request to any element processor having a memory, and any element processor. A circuit that reads the transfer data from the storage location having the transfer source address included in the transmitted transfer request in response to the transfer request transmitted from the sessa, and the transfer destination address included in the transmitted transfer request. A circuit for transmitting the read data together with the transfer destination address to any of the element processors having a memory for main memory to which it belongs, and in response to the transfer destination address and the data transferred from any of the element processors. A circuit for writing the transferred data to a memory location having the transferred transfer destination address in the main memory of each of the element processors.