JPH02189049A - Line controller - Google Patents

Abstract

PURPOSE:To prevent the occurrence of overrun and underrun by separating management information between a transmission/reception buffer main body and a transmission/reception buffer, storing the management information in a memory provided at the location of a line control section to be accessed fastest and providing a bus access control circuit between the memory and the transmission/reception buffer. CONSTITUTION:Buffer management information 6000 is stored in a 2nd reception buffer memory 250. A bus access control circuit 500 in order to isolate electrically and logically internal buses 502, 504, can read the buffer management information of a reception line control section 200 in parallel even while a reception DMAC 260 transfers the received data in a 1st reception buffer memory 290 to a main memory 800 via the internal bus 504. Thus, no overrun takes place even to the received data from a high speed line. This is similarly applied to the transmission side.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a line control device, and particularly to an improvement in processing capacity,
The present invention relates to a line control device that enables improved reliability.

[Conventional technology]

Conventionally, as an example of providing one-procedure processing processors for transmitting and receiving signals in order to improve the processing capacity of line control equipment, I. 81 P
roceedings, 5ession23B, Pap
An example of this is the CCITT (International Telegraph and Telephone Consultative Committee) Na3 common line signal processing device shown in Figure 6 of er4, 1981).

This device uses a microprocessor, ROM,
It consists of RAM, SIO (peripheral LSI for line control), etc., and the transmitting and receiving sides are PIO (peripheral LSI for parallel input/output).
SI).

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the case where the line speed increases, and when connecting to a high-speed line, the SIO
When the data transfer rate (amount of data transferred per unit time) between the CPU and the transmitting/receiving buffer in RAM increases, the bus usage rate increases, causing the CPU to hold and making it difficult to perform procedural processing. .

In addition, in order to transfer data to and from the buffer at high speed, DM A C (Direct Memory Ac
cessController), the corresponding D
When the MAC takes in management information such as the address of the transmitting/receiving buffer from memory, it waits for the bus to become free, which causes so-called overrun errors that cause data to be lost during reception, and so-called under-run errors that occur when sent data is lost during transmission. There was also the problem that run errors occurred and reliability decreased.

An object of the present invention is to solve the above-mentioned problems in the conventional technology, to enable memory access of the procedure processing CPU and DMAC even when connected to a high-speed line, to improve procedure processing ability, and to prevent overruns and underruns. An object of the present invention is to provide a line control device capable of eliminating the occurrence of runs.

[Means to solve the problem]

The above-mentioned object of the present invention is to provide a reception line control section connected to a reception line, a transmission line control section connected to a transmission line, means for connecting a host processor or other line control device, and a transmission procedure processing processor. .

In a line control device having a reception procedure processor, a transmission buffer, a reception buffer, and an internal bus connecting these, a communication means is provided between the transmission procedure processor and the reception procedure processor, and information for managing the transmission buffer. and information for managing the receive buffer, the transmit buffer.

A line control device characterized in that an internal bus access control circuit is provided for storing data in a memory means separate from a receiving buffer, and for making each of the memory means, the transmitting buffer, and the receiving buffer independently accessible. achieved.

[Effect]

In the line control device according to the present invention, the transmission/reception buffer main body and the management information of the transmission/reception buffer are separated, and the management information is stored in a newly provided memory at the fastest accessible position of the line control unit. A bus access control circuit is provided between the transmitter and transmitter/receiver buffer memory.

Specifically, a feature is that buffer management information 6000 shown in FIG. 3 is stored in the second receiving buffer memory 250 shown in FIG. The reception line control unit 200 shown in FIG. 1 reads the buffer management information on the second reception buffer memory 250 and stores the reception data in the buffer 6100 on the first reception buffer memory 290 indicated by the buffer pointer.

The reception procedure processing CPU 270 performs procedure processing on received data. After the procedure processing is completed, the received data is sent to the receiving DMAC.
260, the data is transferred to the main memory 800 via the system bus 600, then processed by the main CPU 700, and transferred to the host computer 2000, which will be described later, via the channel 3000 by the upper device interface channel adapter 900.

The bus access control circuit 500 includes internal buses 502 and 50.
In order to electrically and logically separate the
260 is transferring the received data on the first reception buffer memory 290 to the main memory 800 via the internal bus 504, the reception line control unit 20
0 buffer management information can be read. This prevents overrun even with data received from a high-speed line.

The same applies to the sending side.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, a first example will be described.

FIG. 2 shows a line control device 100 which is an embodiment of the present invention.
1 is a diagram illustrating a configuration example of a communication control device 1000 including: FIG.

The communication control device 1000 shown in this embodiment has a channel 30.
00 to the host computer 2000. The communication control device 1000 includes a plurality of line control devices and a main CPU 700. The main memory 800 is configured by connecting a channel adapter 900 for an upper device interface with a system bus 600.

FIG. 1 shows a configuration diagram of the above-mentioned line control device 100.

The line control device 100 shown in this embodiment has a transmitting system and a receiving system configured symmetrically, and the two are connected by a common memory 400 and a bus access control circuit 545. The configuration and operation of the receiving system will be described below as an example.

First, the configuration of the receiving system will be explained.

The receiving system is connected to the main CPU 7 via the system bus 600.
00 and the main memory 800, a reception DMAC 260 that exchanges signals and data, and a first reception buffer memory 2 that stores data received from the reception line 4000.
90. A reception procedure processing CPU 270 that performs reception procedure processing using the data in the first reception buffer memory 290.
A reception procedure memory 280 that stores the program and work area of the reception procedure processing CPtJ 270. Flag synchronization of received data.

A receiving line control unit 200 that detects FCS errors and transfers them to a buffer. It consists of a second reception buffer memory 250 that stores buffer management information of the reception buffer, and these are connected to the bus access control circuit 500 505, 5, 10 .
515 to internal buses 502.504.512.

Among the above components, the receiving line control unit 200, the receiving DMAC 260, and the receiving procedure processing CPU 270 can be the main body (bus master) that reads and writes to the memory.
The reception line control unit 200 includes a second reception buffer memory 2
50 and the first reception buffer memory 290, the reception DMAC 260 can access the first reception buffer memory 290, and the reception procedure processing CPU 270 can access the reception procedure memory 280. First reception buffer memory 290.
Common memory 400 and second reception buffer memory 25
0, respectively.

Bus access control circuits 500, 505, 510, 515
The gate opens to the memory only when the above bus master accesses the memory via the bus access control circuit, and when accessing the memory without going through the bus access circuit, the gate opens to the bus on the opposite side of the bus access circuit. It has the function of closing the gate to eliminate any impact on the bus.

For example, even if the receiving DMAC 260 is accessing the first receiving buffer memory 290 using the internal bus 504 via the bus access control circuits 505 and 515, the bus access control circuit 510 operates.

It does not affect the internal bus 512. Therefore, reception procedure processing CPU 270 can access reception procedure memory 280 via internal bus 512 and bus access control circuit 510. At the same time, the reception line control section 200 can access the second reception buffer memory 250 via the internal bus 502.

An example of a data structure for storing received data is shown in FIG. The data structure is divided into a buffer 6100 that stores the received data itself and buffer management information 6000, and the buffer management information 6000 has a chain pointer 6010. which is the address of the primary buffer management information. Buffer pointer 60 which is the start address of buffer 6100
20. Data length 60 indicating the effective data length in the buffer
30, and a status 6040 that stores the status of the reception line control unit 200 at the time of completion of reception.

The buffer management information 6000 is stored in the second reception buffer memory 250, and the buffer is stored in the first reception buffer memory 290.

Next, the operation of the receiving system will be explained.

Received data having a format as shown in FIG.
The aforementioned reception line control unit 200 via the reception line 4000
, the reception line control unit 200 detects the flag, recognizes the reception of data, and stores the data in the second reception buffer memory 250 from the address of the buffer management information held within the reception line control unit. The buffer management information 6000 is read.

The reception line control unit 200 extracts the aforementioned buffer pointer 6020 from the read buffer management information 6000, and transfers information from the address of the reception data to the first reception buffer memory 290 pointed to by the buffer pointer. At this time, the chain pointer 6010 of the read buffer management information 6000 is held as the address of the buffer management information to be read next.

When the transfer of the received data is completed, the reception line control unit 200
stores the data length 6030 and reception end status in the buffer management information 6000. The length of the received data is
If the size of the buffer 6100 is changed, it is stored in the primary buffer.

Regarding the received data stored in the first receiving buffer memory 290, the receiving procedure processing CPU 270 first processes the buffer management information 600 in the second receiving buffer memory 250.
Read the status 6040 in 0 and confirm that there is no FCS error or the like. If there is no error, the address and control section of the received data in the first receiving buffer memory 290 are read out and the procedure is processed.

Data common to sending procedure processing during procedure processing.

For example, state variables, send/receive sequence numbers, etc.

The data is stored in the common memory 400. An example of the data structure of common variables in the common memory 400 is shown in FIG.

In order to prohibit simultaneous writing of common variables, a semaphore flag is provided for all common variables, and access is made according to the procedure shown in FIG. That is, the semaphore flag=''1''' is used to mean "in use" and RO11 is used to mean "free", and the portion a in FIG. 6 is performed in one memory access cycle.

After the procedural processing is completed, the receiving procedure processing CPU 270 activates the receiving DMAC 260 and transfers the information portion of the received data for which the procedural processing has been completed to the main memory 800 via the system bus 600. After main memory transfer, main CP
The U 700 activates the upper-level device interface channel adapter 900 and transfers the data to the host computer 2000 via the channel 3000.

According to the above embodiment, the process on the transmitting side is also performed by the host computer 2000 in the reverse procedure to the process on the receiving side. Since the receiving circuit control unit 200 can read the buffer management information 6000 in the second receiving buffer memory 250 even while it is being transferred to the main memory 800 via the internal bus 504 and the receiving DMAC 260,
during buffer chain.

It is possible to prevent an error in which the address of the next receive buffer cannot be read due to bus contention, resulting in a buffer overrun.

Next, a second embodiment will be described.

FIG. 7 shows the common memory 400 in FIG.
A configuration example in which O buffers 410 and 420 are replaced is shown. The FIFO buffer 410 is a reception procedure processing CPU 2
70 to the transmission procedure processing CPU 370, and the FIFO buffer 410 stores control information in the opposite direction.

The above control information is as follows: (1) P/F = 1 bit reception notification (2) Transmission state variable V(S) change notification etc. can be considered as procedural processing.

In the reception and transmission procedures in this embodiment, the common memory access part of the first embodiment described above is changed to a process of transferring to a FIFO buffer, and the procedure processing CPU performs reading from the FIFO buffer. This embodiment is the same as the first embodiment shown above except that .

According to this embodiment, in addition to the effects of the first embodiment shown above, since there is no need to wait for the right to use common data on the common memory, the waiting time of the transmitting/receiving procedure processor is eliminated, and the processing capacity is further improved. It has the effect of improving

It goes without saying that the above embodiment is shown as an example of the present invention, and that the present invention is not limited thereto.

〔Effect of the invention〕

As described above, according to the present invention, the transmission/reception buffer main body and the management information of the transmission/reception buffer are separated, the management information is stored in a newly provided memory in a position of the line control unit that can be accessed at the fastest speed, and A bus access control circuit is provided between the memory and the transmitting/receiving buffer memory, allowing the procedural processing CPU and DMAC to access the memory even when connected to a high-speed line, improving procedural processing ability and preventing overruns and This has the remarkable effect of realizing a line control device that can eliminate the occurrence of underruns.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a line control device that is an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a communication control device including the line control device of the embodiment, and FIG. 3 is a diagram of the data structure of a buffer. FIG. 4 is a diagram showing an example of the format of received data. FIG. 5 is a diagram showing an example of the data structure of common data. FIG. 6 is a flowchart showing an example of the common data access procedure. FIG. 7 is a configuration diagram of a line control device showing another embodiment. 100: line control device, 200: reception line control unit, 25
0゜290: Reception buffer memory, 300: Transmission line control unit, 350, 390: Transmission buffer memory, 2
60: Reception DMAC, 270: Reception procedure processing CPU,
360: Transmission DMAC 2370: Transmission procedure processing CPU
, 400: Common memory, 410, 420: FI
FO buffers, 500 and 505, 510, 515
: Bus access control circuit, 550 and 555, 56
0,565: Bus access control circuit, 600 System bus, 700: Main CPU, 800: Main memory, 1000: Communication control device, 4000: Receiving line,
5ooo: Transmission line.

Claims (1)

[Claims] 1. A reception line control unit connected to a reception line, a transmission line control unit connected to a transmission line, means for connecting to a host processor or other line control device, and a transmission procedure processing processor. , a reception procedure processor, a transmission buffer,
In a line control device having a reception buffer and an internal bus connecting these, a communication means is provided between the transmission procedure processor and the reception procedure processor, and information for managing the transmission buffer and information for managing the reception buffer are transmitted. The transmitting buffer and the receiving buffer are stored in memory means separate from the transmitting buffer and the receiving buffer, respectively, and an internal bus access control circuit is provided which allows each of the memory means and the transmitting buffer and the receiving buffer to be accessed independently. line control device. 2. The line control device according to claim 1, wherein the inter-processor communication means is a common memory. 3. The line control device according to claim 1, wherein the inter-processor communication means is a FIFO buffer. 4. The line control device according to claim 1, wherein the memory means is directly connected to the transmission line control section and the reception line control section, respectively.