JPS5555643A - Memory unit for data reception - Google Patents

Memory unit for data reception

Info

Publication number
JPS5555643A
JPS5555643A JP12838178A JP12838178A JPS5555643A JP S5555643 A JPS5555643 A JP S5555643A JP 12838178 A JP12838178 A JP 12838178A JP 12838178 A JP12838178 A JP 12838178A JP S5555643 A JPS5555643 A JP S5555643A
Authority
JP
Japan
Prior art keywords
circuit
buffer
data
memory unit
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12838178A
Other languages
Japanese (ja)
Other versions
JPS5759700B2 (en
Inventor
Katsuo Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12838178A priority Critical patent/JPS5555643A/en
Publication of JPS5555643A publication Critical patent/JPS5555643A/en
Publication of JPS5759700B2 publication Critical patent/JPS5759700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
    • H04L13/02—Details not particular to receiver or transmitter
    • H04L13/08—Intermediate storage means

Abstract

PURPOSE:To suppress ineffective storage, by inspecting the data through the provision of buffer circuit before and after the assembly circuit for data formation stored in the memory unit and controlling the storage with the memory control circuit. CONSTITUTION:Every time when the new data in 1-bit is received at the buffer 12, data is delivered to the assembly buffer 7, and 8-bit is stored with serial parallel conversion, it is transferred to the line buffer 8. When the count of the bit counter 6 is 32 at transfer, the full data in 32-bit of the line buffer 8 is stored to the memory unit 10 via the memory control circuit 9. In this case, the reception data of the buffer 12 is inspected 5 and if it is not thrown away flag, it is stored to the memory unit 10 through the indication to the memory control circuit 9. In case of line failure, the reception circuit 3 informs the detection to the interruption circuit 11 in case of line failure and if thrown-away-flag, the flag detection circuit 5 does it, and the interruption circuit 11 stores the status information to the memory unit via the memory control circuit 9.
JP12838178A 1978-10-20 1978-10-20 Memory unit for data reception Granted JPS5555643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12838178A JPS5555643A (en) 1978-10-20 1978-10-20 Memory unit for data reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12838178A JPS5555643A (en) 1978-10-20 1978-10-20 Memory unit for data reception

Publications (2)

Publication Number Publication Date
JPS5555643A true JPS5555643A (en) 1980-04-23
JPS5759700B2 JPS5759700B2 (en) 1982-12-16

Family

ID=14983402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12838178A Granted JPS5555643A (en) 1978-10-20 1978-10-20 Memory unit for data reception

Country Status (1)

Country Link
JP (1) JPS5555643A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223750A (en) * 1988-07-13 1990-01-25 Iwatsu Electric Co Ltd Data sink

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199423A (en) * 1975-02-28 1976-09-02 Oki Electric Ind Co Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199423A (en) * 1975-02-28 1976-09-02 Oki Electric Ind Co Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223750A (en) * 1988-07-13 1990-01-25 Iwatsu Electric Co Ltd Data sink

Also Published As

Publication number Publication date
JPS5759700B2 (en) 1982-12-16

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