JPS6116356A - Signal information scanning system - Google Patents

Abstract

PURPOSE:To make a control system possible to scan signal information without ineffective processings, by using a first in first out memory (FIFO) in the input part of signal information and transmitting the output ready signal of the FIFO as an interrupt signal to the control system. CONSTITUTION:A write signal of input signal information 101 is transmitted to an FIFO300 through a signal line 102. Input signal information 101 for which the write signal is transmitted through the signal line 102 is stored in the FIFO300. When data inputted to the FIFO300 appears in the output of the FIFO300, data is transmitted to a format converting circuit 400 through a signal line 301, and the output ready signal of the FIFO300 is transmitted to the control system omitted in the figure through an interrupt signal line 402, and the control system starts scanning input signal information 101 when receiving the interrupt signal through the interrupt signal line 302.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a signal information scanning method for a signal processing device. After scanning a certain point on the target and checking the presence or absence of valid signal information by a change in the flag or focus pattern, it is possible to start scanning the signal information, read the input signal regardless of the presence or absence of a valid signal, and then check the validity. It was a method to check. For this reason, a certain location must be periodically scanned regardless of the presence or absence of valid signal information, which poses the problem of invalidating the scanned content until valid signal information is input. .

<Means for Solving the Problems> The signal information scanning method according to the present invention is intended to solve the above-mentioned conventional problems. In the signal information scanning method of the processing device, there is a first-in-first-out memory that stores input signal information, and an input that detects valid input signal information from among various signals and generates a write signal to the first-in-first-out memory. It consists of a signal detection circuit and a format conversion circuit that performs interface matching between the output format of the first-in-first-out memory and the control system, and converts the output ready signal of the first-in-first-out memory into an interrupt signal to the control system. It is an object of the present invention to provide a signal information scanning method characterized by eliminating invalid processing and simplifying signal processing by configuring the signal to be transmitted as a signal.

<Operation> The signal information scanning method according to the present invention uses the above-described configuration to determine a valid input signal by the input signal detection circuit, and uniquely provides valid input section information in the signal information input section. The output ready signal, which is stored in the first-in-first-out memory and is output only when there is valid information in the first-in-first-out memory, is used as an interrupt signal to the control system, and only when there is valid signal information. The control system performs scanning.

<Example> Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a pronk diagram showing one embodiment of the present invention. In the figure, 100 is an input signal detection circuit (hereinafter referred to as DET) that detects valid input signal information from various input signals and generates a write signal to a first-in-first-out memory (hereinafter referred to as FIFO), which will be described later. , 200 is a read signal generation circuit (hereinafter referred to as SOG) that sends a read signal to 9 FIFO according to a command from the control system;
00 is a FIFo that stores valid input signal information detected by the DET 200, and 400 is a format conversion circuit (hereinafter abbreviated as FCON) that converts the output of the FIFO into a control system format.

In the figure, 101 is an input signal information line, 102 is a signal line, and 2
01 is a control signal line, 202 is a read signal line, 301 is a signal line, 302 is an interrupt signal line, and 401 is an information line.

The operation of an embodiment of the present invention constructed in this manner will be described below, but for convenience of explanation, the input signal will be described as having a 48-pin configuration, and the interface with the control system will be described as having an 8-pin configuration.

In this example, one bit of the 48-bit input signal information line 101 is used as input signal control information, and when the focus is "1", the other 47 bits of signal information are valid, and when the focus is "0", they are invalid. It is said that there is.

Then, the DET 100 receives 1 bit of control information from the input signal information line 101, and the control information is "
A change from 0 to "1" is monitored, and when a change is detected, a write signal of the input signal information 101 is sent to the FIFO 300 via the signal line 102.

FIFO 300 stores input signal information 101 in its own memory when a write signal is sent via signal line 102. The data input to FIFO300 is
300, the data is sent to the FCON 400 via the signal line 301' (r) and the FI
The output ready signal of FO300 is the interrupt signal line 30
When the interrupt signal is received via the interrupt signal line 302, the control system starts scanning the input signal information 101.

A read control signal line 201 from the control system specifies which of six blocks, each of which is divided into 8 pins, is to be read out. When the six gross blocks are sequentially designated by the read control signal line 201, the 48-bit data is divided into 8-bit blocks by the FCON 400 and sequentially sent to the control system via the information line 401. Furthermore, when the sixth block is specified by the control signal line 201, the 5OG 200 sends out a read signal to the FIFO 300 via the signal line 301. Here PIFO30
If there is data waiting within 0, an output ready signal is output again via the interrupt signal line 302, and an interrupt signal is sent to the control system.

If there is no valid data in the FIFO 300, no interrupt signal is sent.

In addition, in the above description, the input signal information line 101 has a focus configuration, F
Although the output information line 401 from CON 400 has been described as having an 8-bit configuration, it goes without saying that these configurations can be set arbitrarily.

<Effects of the Invention> As explained above, the signal information scanning method according to the present invention uses a first-in first-out memory in the signal information input section, and transmits the output ready signal of the first-in first-out memory to the control system. By sending the signal as an interrupt signal to the control system, it is possible to realize that the control system performs signal information scanning without invalidation processing.

This has a huge effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 100... Input signal detection circuit (DET) 101...
- Input signal information line 102--Signal line 200...Read signal generation circuit (SOG) 201...Control signal line
202... Read signal line 300... First in first out memory (FIFO) 301
...Signal line 302...Interrupt signal line 400...Format conversion circuit (FCON) 401
...information line

Claims (1)

[Claims] In the signal information scanning method of a signal processing device having a control system capable of interrupt processing, a first-in-first-out memory is used to store input signal information, and valid input signal information is detected from among various signals. It consists of an input signal detection circuit that generates a write signal to the first-in-first-out memory, and a format conversion circuit that performs interface matching between the output format of the first-in-first-out memory and the control system. A signal information scanning method characterized by sending an output ready signal of an earth-out memory to a control system as an interrupt signal.