JPH10190640A - Communication circuit and data transmission system using communication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the communication circuit which actualizes a real-time control code synchronized with hardware and a data communication between microprocessors by a Manchester transmission system through only one transmission line and the data transmission system which uses the communication circuit. SOLUTION: A part of transmission and reception data transmitted by using Manchester modulation and demodulation is bits for transmitting and receiving the real-time control code synchronized with the hardware and the rest of data is bits for transmitting and receiving data between processors by using a data buffer and performing read/write with a synchronizing signal for Manchester modulation and demodulation, which are stored in FIFO memories 13 and 23; and the data are connected and separated in time series to perform transmission between the processors 11 (21) through the Manchester transmission line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication circuit for performing interprocessor communication using a Manchester transmission line, and a data transmission system using the communication circuit.

[0002]

2. Description of the Related Art Signal processing in the radar field is performed by a combination of hardware and software. The processing until the target is detected is performed by hardware,
Predicting where the target will reach in the future,
Processing such as calculating a detailed position by referring to map data is performed by a relatively large-scale computer such as an industrial computer. In addition, in order for the indicator to draw a target, it is necessary to transmit data in real time. Conventionally, data transmission for computer processing and data transmission for real-time display on an indicator have been performed separately using independent transmission paths.

[0003] When data is transmitted between two points, serial communication is used to reduce the number of transmission lines. RS232C, GPIB, and SCSI communications are frequently used between computers, and when these processes are completed, the results are transmitted, and when transmitted, processing is performed based on the data. Data transmission is performed. On the other hand, Manchester transmission is used for real-time transmission in hardware. The real time refers to, for example, performing data transmission at a timing synchronized with the operation timing of the radar.
In the case of a pulse Doppler radar, a pulse-like radio wave is radiated into space at a certain fixed period. The frequency and the like must be switched according to this cycle. In Manchester transmission, a real-time control code is transmitted in synchronization with such hardware timing. When serial transmission is performed by hardware, serial data, a clock synchronized with the serial data, and a strobe indicating a data delimiter are required. In order to realize these with one transmission line, a Manchester code (data transition) is used. Coding)
This is performed using

FIG. 3 is a block diagram showing a configuration of an interface with a computer in a signal processing system in the radar field. In the figure, microprocessors 31, 3
2 is used as an interface for causing the computer to perform an operation. The microprocessor 31 converts data detected by hardware into a data format that can be processed by the computer. Is provided for transmitting data transmitted from the microprocessor 31 to the computer. Each microprocessor 31, 3
2 connects the SIOs 35 and 36 to the CPU buses 33 and 34 respectively, and performs communication via a serial transmission line 37 composed of only one data line. SIO
As an example 37, a start-stop synchronous communication circuit is illustrated. On the other hand, the real-time control code is communicated between the Manchester communication circuits 38 and 39 via a serial transmission line 40 provided independently of the transmission line 37. 41, 4
Reference numeral 2 denotes a real-time control code generation circuit.

[0005] In the case of a pulse Doppler radar, pulse-like radio waves are radiated into space at a certain fixed period.

The frequency and the like must be switched in accordance with this cycle. In the Manchester transmission, the real-time control code is transmitted in synchronization with the timing of hardware as described above.

[0007]

The Manchester transmission described above is not suitable for data transmission between microprocessors. Data transmission between microprocessors is performed asynchronously with hardware processing, triggered by the occurrence of an event, such as transmitting the result after a certain processing is completed and performing processing based on the transmitted data. is there. Therefore, used for data communication between microprocessors,
For example, asynchronous transmission is also not suitable for transmitting real-time control codes. Transmission of real-time control code
This is because transmission is performed in synchronization with hardware timing. For this reason, conventionally, data communication was independently performed using separate communication paths.

[0008] The real-time control is used not only for controlling data for transmission, but also for controlling signal processing on received signals. In other words, all radar hardware operates based on this timing, and therefore, data transmission must also be performed in synchronization with this timing.

The present invention has been made in view of the above circumstances, and a communication circuit and a communication circuit capable of realizing data communication between a real-time control code synchronized with hardware and a microprocessor by a Manchester transmission method using only one transmission line. It is an object to provide a data transmission system using a communication circuit.

[0010]

According to the data transmission system of the present invention, a part of transmission / reception data transmitted using Manchester modulation / demodulation is set as bits for transmitting / receiving a real-time control code synchronized with hardware, and the remaining bits are transmitted. ,
It is composed of bits for transmitting and receiving data between processors by reading and writing with a synchronization signal for Manchester modulation and demodulation using a data buffer, and connecting and separating these data in a time series, the processor is connected via a Manchester transmission line. It is characterized by performing inter-transmission. The data buffer is composed of FIFO memory.
A read / write signal is generated by performing a logical operation on a flag indicating an empty state of the FO memory and a synchronization signal used for Manchester modulation / demodulation, and the data is read / written.

A computer for performing data processing;
A control object controlled by a computer is connected via a communication circuit, wherein the communication circuit converts a data generated by the control object into data that can be processed by the computer, and a first microprocessor. A second microprocessor for transmitting data transmitted from the microprocessor to a computer, a data buffer for temporarily storing data transmitted between the microprocessors,
A memory control circuit that generates a read / write signal for the data buffer by performing a logical operation on a signal indicating the data storage state of the data buffer and a synchronization signal used for Manchester code modulation and demodulation; Alternatively, a first latch circuit for holding read / write data for the data buffer, a second latch circuit for latching a real-time control code to be supplied from or to the control target,
A first and second data conversion circuit, and a Manchester data line connecting the first and second data conversion circuits, respectively, for coupling or separating the output from the second latch circuit and for modulating and demodulating the output into a Manchester code. Also features.

A communication circuit according to the present invention comprises: a data buffer in which data for performing inter-processor data transmission is stored; a signal indicating a data storage state in the data buffer; and a synchronization signal used for Manchester code modulation. A memory control circuit that generates a read signal for the data buffer by performing a logical operation on the data, a first latch circuit that holds data read from the data buffer triggered by the read signal generated by the memory control circuit, A second latch circuit in which a real-time control code to be executed is held by the arrival of a synchronization signal used for Manchester modulation; and the first and second latch circuit outputs are combined to convert input parallel data into serial data. Parallel-to-serial conversion circuit and Manchester modulation to the parallel-to-serial conversion circuit output Subjected, characterized by including the Manchester modulation circuit for transmitting data via the Manchester transmission path. Also, a Manchester demodulation circuit for demodulating a Manchester code arriving via a Manchester transmission line, and a Manchester code obtained by the Manchester demodulation circuit are separated into real-time control codes and data for communication between processors, and are converted into parallel signals. A parallel conversion circuit, a first latch circuit in which data for performing inter-processor communication among outputs of the serial-parallel conversion circuit is held with a synchronization signal used as a trigger as a trigger, A second latch circuit for holding a real-time control code, a data buffer for storing data for performing inter-processor data transmission via the first latch circuit, and a signal indicating a data storage state of the data buffer; And a synchronization signal used for Manchester code demodulation. Also characterized by comprising a memory control circuit for generating a write signal to the data buffer by.

According to the present invention, transmission of a real-time control code controlled by hardware timing and data communication between microprocessors can be realized by one transmission line.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 and 21 are microprocessors. The microprocessor 11 is provided for converting data detected by hardware into a form that can be processed by a computer.
Is for sending data transmitted from the microprocessor 11 to a relatively large computer such as an industrial computer. The microprocessors 11 and 21 are connected to the FI through the CPU interfaces 12 and 22, respectively.
The FO memories 13 and 23 are connected. FIFO (Fir
St-In First-Out) memory
DT CMOS parallel FIFO (IDT720)
5) is used, and an empty flag EF is incorporated.
16 and 17 are latch circuits. The latch circuit 16 has F
Data read from the IFO memory 13 is held in synchronization with the timing of a read signal output from a read signal generation circuit 14 composed of an inverter and an AND gate,
The latch circuit 17 holds a real-time control code in synchronization with the arrival of a synchronization signal SYNC generated for Manchester modulation. The read signal generation circuit 14
The O memory 13 is constituted by a logic circuit that takes a logical product condition (negative logic) of a signal obtained by inverting the empty flag EF in the inverter gate by the inverter gate and the above-mentioned synchronization signal SYNC.
Reference numeral 18 denotes a parallel / serial conversion circuit (P / S). Latch circuits 16 and 17 are cascaded to the parallel-to-serial conversion circuit 18, where the FIFO data and the real-time control code are connected in time series and supplied to the Manchester modulation circuit 19.

The signal modulated by the Manchester modulation circuit 19 is supplied to a Manchester decoding circuit 29 via only one data transmission line 10. The internal configurations of the Manchester modulation circuit 19 and the demodulation circuit 29 are illustrated in FIG. In the figure, (a) shows a Manchester code data waveform, (b) shows a modulation circuit, and (c) shows a schematic internal configuration of a demodulation circuit. Manchester code always causes a state change near the center of the bit interval. That is, if the data is “1”, the change is “High” and “Low”, and if the data is “0”, the change is from “Low” to “High”. Modulation of the Manchester code is used to clock the flip-flops.
This is done by using exclusive ORs and creating a clock whose phase is inverted. One exclusive OR is required for demodulating the Manchester code, and data and a clock are used for the input. Since the principles of Manchester modulation and demodulation are well known in the art and do not directly relate to the gist of the present invention, further description will be omitted.

The Manchester decoding circuit 29 is supplied with a synchronizing signal SYNC for demodulation. The demodulated data is converted into parallel data via a serial / parallel conversion circuit S / P 28, where it is separated. The obtained data is supplied to the latch circuits 26 and 27, respectively. The data held in the latch circuit 26 is stored in the FIFO at the timing of the signal WRITE generated by the write signal generation circuit 24.
The data is supplied to the memory 23. The write signal generation circuit 25
It is configured by a logic circuit that takes a logical product (negative logic) of a result obtained by inverting the content of the empty flag EF built in the FIFO memory 23 and the demodulation synchronization signal SYNC.

The data held in the latch circuit 27 is output as a real-time control code to an indicator (not shown) that requires real-time control.

Hereinafter, the operation of the embodiment of the present invention shown in FIG. 1 will be described in detail.

Data generated by a computer (not shown) is supplied to a microprocessor 11. The data received by the microprocessor 11 is sequentially buffered in the FIFO memory 13 via the CPU interface circuit 12. Area empty information for buffering in the FIFO memory 13 is always displayed by a built-in empty flag (EF). The buffer FULL reads data buffered in the FIFO memory 13 when a synchronization signal (SYNC) for Manchester modulation arrives from the outside, and is held in the latch circuit 16. On the other hand, real-time control codes are generated and held in the latch circuit 17 by hardware (not shown). The latch circuits 16 and 17 are cascaded, and the combined data is loaded into the parallel-to-serial conversion circuit 18 and converted into serial data in synchronization signal units supplied for Manchester modulation.
The serial data generated here is supplied to the Manchester modulation circuit 19 shown in FIG. 2, and the data modulated here is supplied to the Manchester demodulation circuit 29 on the receiving side via the Manchester data line 10.

The serial data demodulated by the Manchester double tone circuit 29 whose outline is shown in FIG. 2 is supplied to a serial / parallel conversion circuit 28, where the data converted into parallel data is used for communication data between processors and real-time control. And latch circuits 26, 2
7 and held there. Here, the timing at which the data is held is determined by the synchronization signal SYN generated for demodulation.
According to C. The inter-processor communication data held in the latch circuit 26 is stored in the FIFO memory 23 based on a write signal generated by the logic circuit 25. The write signal is generated as a trigger for writing data when the empty flag is checked by checking the empty flag and a synchronization signal arrives. The data stored in the FIFO memory 23 is taken into the microprocessor 21 via the CPU interface circuit 22 and transmitted to a computer (not shown) for processing. on the other hand,
The real-time control code held in the latch circuit 27 is supplied to hardware (not shown) to perform desired hardware processing. As described above, the present invention realizes data communication between the real-time control code and the microprocessor with one transmission line. To this end, a FIFO memory, a latch circuit, and a logic circuit are added to the components of this type of apparatus (Manchester transmission), thereby reducing the number of parts and reducing the cost of the system. Can be built.

[0021]

As described above, the present invention provides a communication circuit and a communication circuit capable of realizing data communication between a real-time control code synchronized with hardware and a microprocessor by using only one transmission line by the Manchester transmission method. The present invention provides a data transmission system used.

A field in which processing up to the detection of a target is performed by hardware, and processing such as prediction of a position that the target will reach in the future and calculation of a detailed position by comparing it with map data is realized by a computer. For example, the effect obtained in the signal processing in the radar is great, the number of parts can be reduced, and the resulting effect of improving the reliability can be obtained, so that the system configuration can be constructed at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram cited for explaining a modulation / demodulation operation for realizing Manchester transmission, which is adopted in the present invention.

FIG. 3 is a diagram cited for explaining data exchange between a radar system and a computer in the related art.

[Explanation of symbols]

10: Manchester transmission line, 11, 21: microprocessor, 13, 23: FIFO memory, 14, 24: read / write signal generation circuit, 16, 17, 26, 27 ...
Latch circuit, 18, 28 ... parallel / serial conversion circuit, 19, 2
9: Manchester modulation / demodulation circuit.

Claims (5)

[Claims] 1. A part of transmission / reception data transmitted using Manchester modulation / demodulation is used as a bit for transmitting / receiving a real-time control code synchronized with hardware, and a remainder is a synchronization signal for Manchester modulation / demodulation using a data buffer. Data transmission and reception by transmitting and receiving data between processors by reading and writing data, and connecting and separating these data in a time-series manner to transmit data between processors via a Manchester transmission path. system. 2. The data buffer comprises a FIFO memory, and generates a read / write signal by performing a logical operation on a flag indicating an empty state of the FIFO memory and a synchronization signal used for Manchester modulation / demodulation. 2. The data transmission system according to claim 1, wherein read / write is performed. 3. A logical operation of a data buffer in which data for performing data transmission between processors is stored, a signal indicating a data storage state in the data buffer, and a synchronization signal used for Manchester code modulation. A memory control circuit for generating a read signal for the data buffer, a first latch circuit for holding data read from the data buffer triggered by the read signal generated by the memory control circuit, and a real-time control code arriving from the outside. A second latch circuit that is held by the arrival of a synchronization signal used for Manchester modulation, and a parallel / serial circuit that combines the first and second latch circuit outputs and converts input parallel data into serial data Manchester modulation is applied to the output of the conversion circuit and A communication circuit comprising a Manchester modulation circuit for transmitting data via a transmission line. 4. A Manchester demodulation circuit for demodulating a Manchester code arriving via a Manchester transmission line,
A serial-parallel conversion circuit that separates the Manchester code obtained by the Manchester demodulation circuit into a real-time control code and data for inter-processor communication and converts it into parallel signals, and data for performing inter-processor communication among serial-parallel conversion circuit outputs A first latch circuit for holding a synchronization signal used for demodulation as a trigger, a second latch circuit for holding a real-time control code of the serial-parallel conversion circuit output, and the first latch circuit A data buffer for storing data for performing inter-processor data transmission via a processor, a signal indicating a data storage state of the data buffer, and a synchronization signal used for Manchester code demodulation are logically operated. A memory control circuit for generating a write signal to the buffer. Communication circuit to be. 5. A computer that performs data processing and a control target that is controlled by the computer are connected through a communication circuit, and the communication circuit converts data generated by the control target into data that can be processed by the computer. A first microprocessor, and a second microprocessor for transmitting data transmitted from the first microprocessor to a computer.
Microprocessor, a data buffer for temporarily storing data transmitted between the microprocessors, and a logical operation of a signal indicating a data storage state of the data buffer and a synchronization signal used for Manchester code modulation / demodulation. A memory control circuit for generating a read / write signal for the data buffer, a first latch circuit for holding read / write data from the data buffer or for the data buffer, and a control target or supply to the control target. A second latch circuit for latching a real-time control code, a first and second data conversion circuit for coupling or separating the outputs of the first and second latch circuits, and modulating and demodulating the output to a Manchester code; Manchester data line connecting the second data conversion circuit Data transmission system, characterized in that consisting of.