JPS60207946A - Data transfer control system - Google Patents

Abstract

PURPOSE:To shorten a time up to data transfer by generating immediately a command from an interrupted processor in case of data transfer using a communication connecting adaptor. CONSTITUTION:When a writing command W+RQ from a processor CPU1 is set up in an instruction register CMR1, a microprocessor 8 is interrupted, and when the microprocessor 8 discriminates the writing command, a writing interruption request TQ(W) is sent to a processor CPU2. If the interruption is acceptable, the processor CPU2 sets up a reading command R in an instruction register CMR2 and the processor 8 reads out data from a memory 4 and stores the data in a memory 5. When the writing command W+RQ from the processor CPU2 is set up in an instruction register 216, the processor 8 is interrupted and the writing interruption request RQ(W) is sent. If writing is impossible, a nagative acknowledge command N-DMA is set up in an instruction register CMR1.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data transfer control method, and in particular, a communication connection adapter is provided between mutually independent processing devices, thereby controlling data transfer between processing edges. It relates to a method for carrying out.

(b) Prior art and problems In general, when data is transferred between independent processing devices,
A communication connection adapter is provided between the meat processing devices, the write command or read command from the processing device that has generated the data transfer request is held in this communication connection adapter, and then the other processing device responds to these commands. A system is adopted in which when a read command or a write command is sent in a manner such that a communication connection adapter transfers data between meat processing apparatuses.

Here, in the conventional example, the processing device issues a command.
An interrupt/1 request (R
Q), and a command is issued only when the other party's processing device sends a signal indicating that it can accept this interrupt request (+<Q). Conventionally, there have been two methods for processing this interrupt request (RQ).

FIG. 1 is a diagram showing a first conventional example, and in the figure, CI)
Ul and CPU2 are processing units, and CCA is a communication connection adapter. The example of FIG. 1 shows a scheme in which both processing units can generate interrupt requests (RQ) for writes/reads. The figure shows a case where interrupt requests (RQ) from both sides are received by the communication connection adapter at the same time. In this case, the communication connection adapter receives both interrupt requests (RQ)
) and causes each processing device to reissue an interrupt request (RQ). Then, in each processing device, an interrupt request (R
Q) The time it takes to reissue is set to be different. For example, the processing device cPU1 waits for a time t1, and the processing device CPLI2 waits for a time t4.

Here, if 11<12, the processing device CI) U l
The interrupt request (RQ) from the processing unit CI) will be reissued first, and the interrupt from the processing unit CI) will be accepted.

A disadvantage is that a different program must be created for each processing device.

Furthermore, in response to an interrupt request (RQ), a command is issued only after the other processing device issues an acceptability signal (OK), so there is the problem that it takes time to actually issue a command. There is.

Next, FIG. 2 is a diagram showing a second conventional example, and in the figure,
CPUI (M> is mask side processing unit, CPU2 (S)
is a slave-side processing device, and CCA is a communication connection adapter. In the method shown in Figure 2, only the mask processing device issues an interrupt request (RQ), and data transfer from the slave processing device is executed by the mask processing device issuing a read interrupt request at predetermined intervals. This is how it was done. In the figure, the solid line W-D A i''A is a case where the mask side issues a write command and the slave side issues a read command, and the broken line R-D A T A is a case where the mask side issues a read command.

1 This is the case when the slave side issues a 0 store command.

In the conventional example shown in Fig. 2, a command is issued only after the other processing device issues an acceptable signal (OK) in response to an interrupt request (RQ), so it takes until the command is actually issued. There is a problem that it takes time. Furthermore, even if a transfer request occurs, the slave-side processing device cannot operate without a polling operation from the other party, so there is a drawback that data transfer is slow. Furthermore, since the processing procedures for data transfer differ between the mask side and the slave side, there is a problem in that a different program must be created for each processing device.

(c) Object of the Invention The present invention aims to solve the above-mentioned drawbacks and to enable efficient data transfer between processing devices.

(d) Structure of the Invention In order to achieve the above object, the present invention includes a communication connection adapter that is connected to both a first processing device and a second processing device, and the communication connection adapter allows the first processing to be performed. In a data transfer control method that controls data transfer between a device and a second processing device, a request function is issued from one processing device to generate a write request from one processing device to the other processing device. A1 write command, a read command issued from the other processing device in response to the write command with a request function, and a read command issued by the one processing device to generate a read request from the one processing device to the other processing device. A read command with a request function issued by a processing device, a write command issued from the other processing device in response to the read command with a request function, and a store command with a request function or a read command with a request function. If the other processing device cannot respond to the above, a negative response command issued by the other processing device is prepared, and the communication connection adapter includes:
Command registers for storing the various commands described above are provided independently for the first processing device and the second processing device, and the communication connection adapter receives the write command with request function from one of the processing devices. Or, when a read command with a request function is received, the command is held and a write request or read request is sent to the other processing device, and the other processing device is able to respond to the request. A read command or a write command is sent to the communication connection adapter, and the communication connection adapter executes the data transfer, and if the other processing device cannot respond to the request, it sends the above negative response command and response. The present invention is characterized in that data indicating the reason for non-response is sent to the communication connection adapter, and the communication connection adapter is configured to transfer the data indicating the reason for the non-response.

(B) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 3 is a box diagram showing the operation sequence of one embodiment of the present invention, in which CI)Ul, CI)U2 are processing units, CCA is a communication connection 7 adapter, and W-)RQ is a request function ” write command, RQ(W) is a store interrupt request, and R is a read command.

DATA is transfer data, N-N-1) is negative response command, 1! , ND is a termination request, and N-DNA (positive) is data indicating the reason for non-response.

In FIG. 1, first, the processing device CI) U1 communicates and connects the write command W+RQ with the request function I.
When the command is sent to the J adapter CC, the 1lrl communication connection adapter CCA retains the command in its own device and sends a write interrupt request R to the processing device CPtJ2.
Sends Q(W). If the processing unit CPU2 is capable of accepting interrupts, the processing unit CI)U2 sends a read command R to the communication link CC8. 1ir
IshinrenllI! The i adapter CCΔ performs a data transfer operation after confirming that one command is a store-related command and the other is a reading-related command.

Next, for example, a request function (
=J When receiving the store command W + RQ and sending the hostage interrupt request RQ(W) to the partner processing device CPU1, when receiving the negative response command N-DMA from the partner processing device 1icPU1 (6), Communication connection adapter OC
A sends a termination request END to the processing device 2 without transferring data from the processing device CPU2 to the processing device CPUI.
Send out. After that, the communication connection adapter CCA sends data N-DMATh (bumper full information, hard error information, 1 line error information, soft error 1n report, etc.) from the specified memory area in the processing unit CPUI without indicating the reason for non-response. are successively output and transferred to the processing device 2.

The example in FIG. 3 is an example of the use of the write command W4-RQ with the request device 1j, but when the read command R+RQ with the request function is similarly sent to the dynamic coupling adapter CCΔ, the communication connection adapter CCΔ is used. The CCA holds the command in its own device and sends a read interrupt request RQ(R) to the processing device CPtJ2. If the processing unit CPU2 is capable of accepting interrupts, the processing unit HcPU2 sends a print command l'W to the communication connection adapter CCΔ. To the communication connection adapter CC, one side is a lee write command, and the other side is a write command.
After confirming that it is a j4J cloak, data transfer is performed. In this case, Il transmission data D A i'A flows in the opposite direction to the example shown in FIG.

As described above, in the present invention, the interrupt request is sent to the communication connection adapter together with the command, and the interrupted processing device immediately issues the corresponding command. The time required for transfer is significantly reduced.

FIG. 4 shows a block diagram of a communication connection adapter according to an embodiment of the present invention, in which 1 is a communication connection adapter CCΔ,
2 and 3 are processing devices CPU1. CPU2, 4.5 is a memory, 6.7 is a common lotus, 8 is a microphone 1'' processor, 9.
10 is a control circuit including Jl.

11 is an internal hash, 12 is an internal memory for storing programs etc. for the microprocessor 8, 13.14 is an instruction register CMRI, CMR2, 1, 5.16 is a memory address register MARI, MA indicating the transfer start address.
R2, 17, 18 are hide count registers B that hold the number of transferred bytes CR1, 13cR2, 19, 20 are entry buffer registers IEBRI, E13R2 that hold data transfer end status information/response rejection reason information
, 21 are data buffers, and 22 is a register 13Fc that holds information indicating the direction of data transfer in the data buffer 21. FR, 23, and 24 are data sending buffer gates.

The operation of the embodiment shown in FIG. 4 will be described below in conjunction with the operation sequence shown in FIG.

(2) First, a write command with a request function from the processing device CPtJl is set in the instruction register CMRI. Furthermore, the transfer start address in the memory 4 is set in the memory address register MARI, and the transfer number is set in the note count register. It will be done. The microprocessor 8 analyzes the contents of the instruction register CMR 1, and when it identifies that it is a write command with a request function, sends the command via the interrupt control circuit IO to 'ζ,
Write interrupt request RQ (W
) is sent.

(2) If the processing unit CPU2 is capable of accepting interrupts, it sends the read command 'R to the instruction register CMR2. Further, the transfer start address in the memory 5 is set in the memory address register MAR2. Further, the contents of the hide count register BCR1 are stored in the hide count register BCR2.

■ The microprocessor 8 sequentially reads data from the memory 4 based on the contents of the memory address register MARI and hide count register BCR1.
The data is stored in the data buffer 21 and sent to the data buffer 21.

On the other hand, the microprocessor 8 simultaneously outputs memory 1 address register MΔR2 and byte register B.
Based on the contents of C R 2, date 1 fuhua 2
The data is sequentially read from 1 and stored in the memory 5.

■ Next, the processing unit cpu4 asks the requester f1 and the store command W + R Q is sent to the instruction register CMR.
2, the transfer start address in the memory 5 is set to the memory address register MAR2, and the number of transferred bytes is written to the byte count register BCR2, an interrupt is generated to the microprocessor 8 in the same way as in the above I can't do it. The microprocessor 8 interprets the contents of the instruction register CMR2 and identifies that it is a write command with a request function.
Sends an interrupt request RQ(W) containing 1 to 1.

■ At this time, in the processing unit cpui, interrupt receiver 4
= J ke 11J, the processing unit CPU l sends a negative response command)' N - DMA to the command register CM.
Set to R1. When the microprocessor 8 identifies the negative response command N-DMA, the interrupt control circuit 10
sends an end request END to the processing unit CI) U 2 via .

Furthermore, data N-DMAI indicating the reason for non-response from the processing unit CPUI is stored in the entry buffer register E B
cents to R1. This information is further set in the entry buffer register EBR2 and notified to CPLJ2.

Next, FIG. 5 is a diagram showing an example of an operation sequence when requests (RQ) are received from both the processing devices CPLII and CPU2 at the same time. In this case, the request (RQ) from one of the processing devices (in the illustrated example, CI U 1 ) is canceled and a termination request E is sent to the processing device.
ND and blind interrupt request RQ(W) is sent. The subsequent operations are similar to those shown in FIG.

Note that, although not shown in FIG.
), and a collision detection register for detecting collisions of R
A notification request register is provided for sending Q(W) and Q(R) to the partner processing device.

(F) Effects of the Invention According to the present invention, it is possible to make the programs of two processing devices the same, and the time required from issuing a data transfer request to actually starting data transfer is can be shortened, resulting in improved economy and performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one example of a conventional data transfer sequence between processing devices, FIG. 2 is a diagram illustrating another example of a conventional data transfer sequence between processing devices, and FIG. 3 is a diagram showing one example of a conventional data transfer sequence between processing devices. A diagram showing an example operation sequence, FIG.
FIG. 5, a block diagram of the communication connection adapter of the embodiment, is a diagram showing an example of an operation sequence when requests are received from two processing devices simultaneously. In Fig. 4, ■ is a communication connection adapter, 2゜3 is a processing device, 4 and 5 are memories, 8 is a microphone l:1 sensor,
9.10 is an interrupt control circuit, 13.14 is an instruction register, and 21 is a data buffer. [CPl, /l] [CPt/d] (ccA) Mushroom 10 Slag? prisoner

Claims (1)

[Claims] A communication connection adapter is provided that is connected to both the first processing device and the second processing device, and the communication connection adapter controls data transfer between the first processing device and the second processing device. In the transfer control method, in order to generate a print request from one processing device to the other processing device, a write command with a request function is issued from one of the processing devices, and a write command with the request function is responded to. a read command issued from the other processing device, and a request function ((J read command and , a write command l' issued from the other processing device in response to the read command with the request function example, and the other processing device responds to the resident command with the request function or the read command with the request function. If this is not possible, a negative response command issued from the other processing device is prepared, and a command register for storing the various commands is provided in the communication connection adapter for the first processing device and the second processing device. When the communication connection adapter receives the write command with request function or the read command with request function from the one processing device, the communication connection adapter holds the command (X) and transfers the command to the other processing device. Sends a write request or a read request to the processing device, and when the other processing device is able to respond to the request, sends the read command or write command to the communication connection adapter, and On the other hand, when the other processing device cannot respond to the request, it sends the negative response command and data indicating the reason for the non-response to the communication link 7, A data transfer control system characterized in that the communication connection adapter is configured to indicate the reason for the response rate i=J and to execute the transfer of J data.