JP3615306B2 - Storage device access system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a storage device access system for accessing a storage device that is not connected to an address bus but connected to a data bus from a processor.
[0002]
[Prior art]
Some storage devices are configured not to be connected to an address bus but to capture information such as an address via a data bus. Conventionally, when information is transferred to such a storage device, the processor executes the transfer instruction or the like, or a device such as DMAC that can transfer information autonomously obtains the right to use the bus. There was only a means to transfer autonomously.
[0003]
[Problems to be solved by the invention]
Incidentally, a storage device connected to a processor is generally connected to a data bus with a bit width such as 8 bits, 4 bits, and 1 bit. Therefore, when the data bus has a bus width larger than this, the necessary bus width is secured by arranging the required number of storage devices in parallel.
[0004]
However, it is possible for a processor such as that described above to execute information that exceeds the width of the bus connected to these storage devices (for example, address information or the like usually exceeds the bus width) by a transfer instruction. Therefore, there is a problem that it is necessary to execute a plurality of transfer instructions, which takes time. Also, even if transfer is performed autonomously using DMAC or the like, it is necessary to perform bus arbitration in order to obtain the right to use the bus. There was a problem that it took.
[0005]
From such a point, when information is transferred to the storage device having the above-described configuration, it has been desired to realize a configuration that does not require a bus arbitration function and can be transferred in a short time.
[0006]
[Means for Solving the Problems]
The present invention employs the following configuration in order to solve the above-described problems.
<Constitution>
Are connected via a data bus to the processor, comprising a storage device for receiving a predetermined number of bits of the address information output of the processor, a small storage access than the receivable number of address bits of the memory device the address information A system having an information transfer device connected to the data bus, wherein the processor outputs a write command to the information transfer device and outputs the address information via an address bus; An information storage that outputs a read instruction of a predetermined address to the information transfer device, and the information transfer device fetches and stores the address information output from the processor via the address bus when receiving the write command and parts, performs intake control and receiving the read instruction to the storage device, the address of the previous SL information storage unit Storage access system which comprises a sequence the information transfer unit to be output to the data bus divided broadcast the address bits can be received in the storage device.
[0007]
<Explanation of Claim 1>
A storage device connected to the data bus is a storage device configured to receive information such as address information via the data bus. When address information is transferred to such a storage device, the address information is usually larger than the bus width of the storage device, so that transfer is required a plurality of times.
[0008]
Accordingly, the present invention provides a information transfer device connected to the data bus provided, when accessing the storage device from the processor first, and transfers the address information to the information transfer device, and stores in the information transfer device. Next, the processor issues a transfer command, for example, a read request for a predetermined address. This address is an address determined for the information transfer apparatus to perform an information transfer operation to the storage device. Here, since the processor is a read request, the data bus is free. Therefore, the information transfer device divides and transfers the stored address information to the storage device using the data bus .
[0009]
In this way, address information from the processor is transferred to the storage device. Therefore, even if the address information is the number of bits greater than the bus width of the storage device, the processor does not issue multiple transfer instructions and does not require bus arbitration. Can do.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<Constitution>
FIG. 1 is a block diagram showing a specific example of a storage device access system of the present invention.
The system shown in the figure includes a processor 1, a storage device 2, an information transfer device 3, an address bus 4, a data bus 5, and control lines 6 and 7.
[0011]
The processor 1 controls each part and is connected to the address bus 4, the data bus 5, and the control line 6. The storage device 2 is a storage device that is not connected to the address bus 4 and is connected only to the data bus 5 and the control line 6, and is configured to receive address information, commands, and data via the data bus 5. Storage device.
[0012]
The information transfer device 3 is a device that autonomously transfers information such as address information to the storage device 2 via the data bus 5, and includes an information storage unit 31, an information transfer unit 32, and an end notification unit 33. . The information storage unit 31 is a storage unit that stores information such as address information sent from the processor 1 to the storage device 2, and the information transfer unit 32 has received a read request for a specific address determined in advance from the processor 1. In this case, it has a function of receiving this and transferring the information stored in the information storage unit 31 to the storage device 2 via the data bus 5. That is, in this specific example, when information transfer from the information transfer device 3 to the storage device 2 is performed, a read request is issued from the processor 1 to the information transfer device 3 at a specific address so as to be activated. It is composed. Further, the end notification unit 33 has a function of sending a normal end notification to the processor 1 when the information transfer to the storage device 2 is normally ended. A specific configuration inside the information transfer apparatus 3 will be described later.
[0013]
The address bus 4, the data bus 5, and the control line 6 are ordinary system buses. The control line 7 is a control line for sending a control signal from the information transfer device 3 to the storage device 2.
[0014]
FIG. 2 is a block diagram of the internal configuration of the information transfer apparatus 3.
The decoder 301 decodes the write to the latch instruction address from the processor 1 and the read to the transfer start instruction address via the address bus 4 and the control line 6, and sends a control signal to the latch circuit 302 and the timing generation circuit 303. It is a circuit to send out. The latch circuit 302 is a circuit that latches the contents of the data bus 5 and sends the latched contents to the transfer control circuit 304 when a latch signal is sent from the decoder 301.
[0015]
Upon receiving the transfer start signal from the decoder 301, the timing generation circuit 303 has a function of starting timing and supplying the transfer timing to the transfer control circuit 304 and supplying the control signal change timing to the control signal generation circuit 305. ing. The transfer control circuit 304 divides the data from the latch circuit 302 into a predetermined bus width in accordance with an instruction from the timing generation circuit 303 and sends it to the data bus 5 a predetermined number of times. The function of sending data of normal transfer end to the data bus 5 by the signal from the. Further, the control signal generation circuit 305 sends necessary signals such as a write pulse and a select signal to the storage device 2 for the number of times of transfer in accordance with the instruction of the timing generation circuit 303, and then, in accordance with the signal from the timing generation circuit 303, 1 has a function of sending a transfer acknowledge signal to 1.
[0016]
Next, the operation of this example will be described.
<Operation>
Here, as an operation example, the processor 1 uses a 32-bit microprocessor, has a data bus of 8 bits width as the storage device 2, and includes chip enable (CE), write enable (WE) address latch enable (ALE), and the like. A system in which four EEPROMs having four control lines 7 and receiving 21-bit address information in three portions via the data bus 5 in parallel will be described. That is, this system uses a single 16 Mbit (2 Mbit × 8 bit) EEPROM as the storage device 2 to generate a 32-bit bus width, and 21 bits (= 2M-bit address space information) is sent.
[0017]
FIG. 3 is a sequence chart of information transfer among the processor 1, the information transfer device 3, and the storage device 2 in this case.
FIG. 4 is an explanatory diagram of the usage status of the address bus 4 and the data bus 5 in this case.
[0018]
When the processor 1 accesses the storage device 2, first, the processor 1 performs transfer information write to the information transfer device 3 {(1) in FIG. 3}. At this time, on the address bus 4, as shown in FIG. 4, an address (specific address) indicating a predetermined latch instruction output by the processor 1 is set. On the data bus 5, transfer information (address information 21 bits for the EEPROM) output by the processor 1 is output in a 32-bit width.
[0019]
In the information transfer apparatus 3, the decoder 301 starts decoding by a signal indicating the start of transfer on the control line 6, and the latch instruction address on the address bus 4 and a write signal on the control line 6 cause the latch circuit 302 to Send a latch signal. Thereby, the latch circuit 302 latches the transfer information on the data bus 5 in accordance with the latch signal from the decoder 301. After latching the transfer information, the control signal generation circuit 305 returns a transfer acknowledge to the processor 1.
[0020]
After that, the processor 1 performs transfer activation read with respect to the information transfer apparatus 3 {FIG. 3 (2)}. At this time, as shown in FIG. 4, the address on the address bus 4 is an address indicating a predetermined transfer start output from the processor 1. On the other hand, the data bus 5 is in an empty state because the processor 1 is performing a read operation.
[0021]
In the information transfer apparatus 3, the decoder 301 starts decoding based on a signal indicating the start of transfer on the control line 6, and the timing generation circuit 303 is read based on the transfer start instruction address on the address bus 4 and the read signal on the control line 6. To send a timing creation start signal. The timing generation circuit 303 starts a timing operation in response to the timing generation start signal, and sends a timing signal to the transfer control circuit 304 and the control signal generation circuit 305 at a predetermined timing. The transfer control circuit 304 divides the data latched in the latch circuit 302 by 8 bits from the lower bits in synchronism with the timing signal from the timing generation circuit 303, and provides four data in parallel to the 32-bit width of the data bus 5. Send out three times in a row {FIGS. 3 (3) to (5)}.
[0022]
Accordingly, as shown in FIG. 4, the data D ₀₀ to ₀₇ , D ₀₈ to ₁₅ , and D ₁₆ to ₂₀ latched in the information transfer 1 to 3 are output on the data bus 5. For example, in the case of the information transfer 1, the latched data D ₀₀ to ₀₇ is replaced with the same data in parallel in the 32-bit data bus D ₂₄ to ₃₁ , D ₁₆ to ₂₃ , D ₀₈ to ₁₅ and D ₀₀ to _07. Is sent out. As a result, 21-bit address information is sent as serial data to each EEPROM. Thereafter, normal end data (for example, 00000001H in the present specific example) set in advance is transmitted in a transfer end notification {FIG. 3 (6)}.
[0023]
The control signal generation circuit 305 asserts CE and ALE to the storage device 2 via the control line 7 before the transfer control circuit 304 starts transfer according to the timing signal from the timing generation circuit 303. . Then, WE is asserted to the storage device 2 via the control line 7 in synchronization with the transmission control circuit 304 sending out the data. Thereafter, as shown in FIG. 4, the control signal generation circuit 305 sends a transfer acknowledge to the processor 1 via the control line 6 in synchronization with the transfer control circuit 304 sending normal end data to the processor 1. Send it out.
[0024]
By receiving the transfer acknowledge from the information transfer device 3, the processor 1 reads the normal end data on the data bus 5, thereby ending the transfer start read. Thereafter, the processor 1 accesses the storage device 2 via the control line 6 {FIG. 3 (7)}.
[0025]
<effect>
As described above, according to the storage device access system of the above specific example, a system for transferring information to the storage device 2 connected to the data bus 5 in a short time is provided without providing a bus arbitration function. be able to.
[0026]
<< Explanation of usage form >>
In the above specific example, the address information has been described as the information transferred to the storage device 2, but the present invention is not limited to this, and other information may be used. In addition, the storage device 2 has been described as an example of a configuration that is not connected to the address bus. Further, the configuration of the storage device 2 can be similarly applied to configurations other than the configuration of the above specific example (2M bits × 4 8 bits).
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a specific example of a storage device access system of the present invention.
FIG. 2 is a block diagram of an information transfer device in the storage device access system of the present invention.
FIG. 3 is a sequence chart of information transfer in the storage device access system of the present invention.
FIG. 4 is an explanatory diagram of a bus usage status in the storage device access system of the present invention.
[Explanation of symbols]
1 Processor 2 Storage Device 3 Information Transfer Device 4 Address Bus 5 Data Bus 31 Information Storage Unit 32 Information Transfer Unit

Claims (1)

Are connected via a data bus to the processor, comprising a storage device for receiving a predetermined number of bits of the address information output of the processor, a small storage access than the receivable number of address bits of the memory device the address information A system,
An information transfer device connected to the data bus;
Wherein the processor via the address bus test and outputs a write instruction to the information transfer device to output the address information, and outputs the read command subsequent address that is determined relative to the information transfer device,
When receiving the write command, the information transfer device fetches and stores the address information output from the processor via the address bus, and receives the read command from the storage device. performs write control, and sequentially the information transfer unit to be output to the data bus are divided address information before Symbol information storage unit in the receivable address bits of the memory device,
A storage device access system comprising:

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