JPH03286355A - Microcomputer - Google Patents

Abstract

PURPOSE:To enable an external device to easily decide a ready signal by providing a 1-pulse ready signal generating circuit which produces a ready signal as a 1-pulse signal. CONSTITUTION:A bus interface 3 included in a slave microcomputer 2 is provided with a 1-pulse ready signal generating circuit 10 which produces a ready signal 9 as a 1-pulse signal. Thus an external device (host microcomputer) 1 can easily detect the signal 9 at its rise and fall when the reception of data outputted from the device 1 is informed to the device 1 and when a fact that the data can be sent to the device 1 is informed to the device 1 respectively. Thus a detection circuit of the device 1 is simplified and the cost is reduced for the microcomputers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having a bus interface function for transferring data with, for example, a host microcomputer as an external device.

[Conventional technology]

FIG. 4 is a professional diagram showing the configuration of a computer system using a conventional microcomputer. In FIG. 4, l is a host microcomputer, 2 is a microcomputer that has a built-in bus interface function and operates according to instructions from the host microcomputer 1 (hereinafter referred to as a slave microcomputer), and 3 is a host microcomputer that is built in the slave microcomputer 2. A bus interface for exchanging data between the microcomputer 1 and the slave CPU, 4 the slave CPU built in the slave microcomputer 2, 5 a data bus between the host microcomputer 1 and the bus interface 3, and 6 the bus interface 3. and slave CP
This is a data bus between U and d. 7 is a read signal that controls the operation of the host microcomputer 1 to read data from the bus interface 3;
is output from the host microcomputer 1 and is normally “
When reading from the "H" (high level) state, it changes to the "L" (low level) state, and is used to take in data from the bus interface 3 to the host microcomputer 1 at the rising edge of the "H" state from the "L" state. .8
is a write signal that controls the operation of the host microcomputer l to write data to the bus interface 3, and this write signal 8 is
It is normally output from the "H" state and becomes "L" state during writing, and the bus interface 3 of the slave microcomputer 2 takes in data at the rise of the "H" state from the "L" state. Reference numeral 9 is a ready signal which is a data reception/transmission request signal to the host microcomputer 1, and is a signal that informs the slave microcomputer 2 that it is ready to operate as a slave CPU function to the host microcomputer 1.

Next, the operation of this conventional example will be explained.

5 and 6 are timing charts showing bus control signals and operations of the conventional bus interface function.

FIG. 5 shows the operation of data transfer from the host microcomputer 1 to the slave microcomputer 2. FIG. 6 shows the operation of data transfer from the slave microcomputer 2 to the host microcomputer 1.

Note that in the figure, the microcomputer is abbreviated as microcomputer.

First, the case where data is transferred from the host microcomputer 1 to the slave microcomputer 2 will be described. When the host microcomputer 1 transfers data, the host microcomputer 1 outputs the data to the data bus 5. Furthermore, the write signal 8 is changed from the normal "H" state to the "L" state, and then, upon rising from the "L" state to the "H" state, the data on the data bus 5 is transferred to the bus interface 3 in the slave microcomputer 2. has lunch. When data is launched into the bus interface 3, the ready signal 9 output from the slave microcomputer 2 changes from the "L" state to the "H" state. Next, when the slave CPU 4 reads the data launched to the bus interface 3 via the data bus 6, the ready signal 9 changes from the "H" state to the "L" state.The host microcomputer 1 recognizes that the ready signal 9 is " By reading the change from the "H" state to the "L" state, it can be recognized that the slave CPU 4 has received data.

Next, a case in which data is transferred from the slave microcomputer 2 to the host microcomputer 1 will be described. When the slave CPU 4 writes data to the bus interface 3 via the data bus 6, the ready signal 9 output from the bus interface 3 changes from the "L" state to the "H" state. By reading this change in the ready signal 9, the host microcomputer 1 can determine whether it is time to read data. When the host microcomputer 1 reads data, when the read signal 7 output from the host microcomputer 1 is changed from the normal "H" state to the "L" state, the data is output from the bus interface 3 to the data bus 5, and then the read signal 7 is output from the bus interface 3 to the data bus 5. Data on the data bus 5 is received by the host microcomputer 1 when the signal 7 rises from the "L" state to the "H" state. Further, the ready signal 9 changes from the "H1" state to the "L" state.

[Problem to be solved by the invention]

When the host microcomputer 1 requires the ready signal 9, it informs the host microcomputer 1 that the slave microcomputer 2 has received data output from the host microcomputer 1, and when the slave microcomputer 2 This is the time to notify the host microcomputer 1 that it is ready to send data to the host microcomputer 1. In the conventional ready signal 9, as shown in FIGS. When the slave microcomputer 2 notifies the host microcomputer 1 that the slave microcomputer 2 has received data, the ready signal 9 is at the falling edge, and when the slave microcomputer 2 transmits data to the host microcomputer 1, the ready signal 9 is at the rising edge. As can be seen from this, it is necessary to detect the rise and fall of the ready signal 9 on the host microcomputer l side, which poses a problem in that the detection circuit becomes complicated.

This invention was made in order to solve the above-mentioned problems, and it is necessary to notify the external device that data output from the external device (host microcomputer) has been received, and to send the data to the external device. It is an object of the present invention to provide a microcomputer that allows an external device to easily determine a ready signal that notifies the external device of a state.

[Means to solve the problem]

The microcomputer according to the present invention generates a ready signal 9 and indicates that it is ready to receive data to an external device (host microcomputer 1), and when it becomes possible to transmit data from the external device. In order to indicate this, the present invention is characterized in that it includes a 1-pulse ready signal generation circuit 10 that generates the ready signal 9 as a 1-pulse signal.

[Effect]

When notifying the external device that data output from the external device (host microcomputer 1) has been received;
When notifying the external device that data is to be transmitted to the external device, the 1-pulse ready signal generation circuit 10 generates a 1-pulse ready signal 9. This allows the external device to detect either the rise or fall of the ready signal 9.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a computer system using a microcomputer according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 1, 10 transfers data written by the host microcomputer 1 to the bus interface 3 to the slave C.
When notifying the host microcomputer 1 that the PU4 has read data, and when notifying the host microcomputer 1 that the slave microcomputer 2 is ready to send data to the host microcomputer 1, a one-pulse ready signal is sent to the slave microcomputer. This is a 1-pulse ready signal generation circuit that outputs from 2.

Next, the operation of this embodiment will be explained. FIGS. 2 and 3 are timing charts showing bus control signals and operations of the bus interface function of this embodiment. FIG. 2 shows the operation of data transfer from the host microcomputer 1 to the slave microcomputer 2. FIG. 3 shows the operation of data transfer from the slave microcomputer 2 to the host microcomputer 1.

First, the case where data is transferred from the host microcomputer 1 to the slave microcomputer 2 will be described. When the host microcomputer 1 transfers data, the host microcomputer 1 outputs the data to the data bus 5. Furthermore, the write signal 8 is changed from the normal "H" state to the "L" state, and then, upon rising from the "L" state to the "H" state, the data on the data bus 5 is transferred to the bus interface 3 in the slave microcomputer 2. has lunch. Next, when the slave CPU 4 reads the data launched to the bus interface 3 via the data bus 6, a one-pulse ready signal 9 generated by the one-pulse ready signal generation circuit 10 is output. By reading this ready signal 9, the host microcomputer 1 can recognize that the slave CPU 4 has received the data.

Next, a case in which data is transferred from the slave microcomputer 2 to the host microcomputer 1 will be described. When the slave CPU 4 writes data to the bus interface 3 via the data bus 6, the 1-pulse ready signal 9 generated by the 1-pulse ready signal generation circuit 10 is output from the bus interface 3, and the ready signal 9 becomes 1. A pulse is generated. By reading this change in the ready signal 9, the host microcomputer 1 can determine whether it is time to read data. When the host microcomputer 1 reads data, when the read signal 7 output from the host microcomputer 1 changes from the normal "H'" state to the @L" state, the data is output from the bus interface 3 to the data bus 5, and then When the read signal 7 rises from the "L" state to the "H" state, the data on the data bus 5 is received by the host microcomputer 1.

〔Effect of the invention〕

As described above, according to the present invention, since the tank bottom is equipped with a one-pulse ready signal generation circuit that generates a ready signal as a one-pulse signal, it is possible to notify the external device that data output from the external device has been received. When informing the external device that it is ready to send data to the external device, the external device can easily detect the ready signal on either the rising or falling edge of the ready signal, and this makes it easier for the external device to detect the ready signal. The bottom of the tank can be easily formed and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system using a microcomputer according to an embodiment of the present invention;
Figure 2 is a timing chart showing the operation of data transfer from the host microcomputer to the slave microcomputer using the bus interface function in this embodiment, and Figure 3 is a timing chart showing the operation of data transfer from the slave microcomputer to the host microcomputer using the bus interface function in this embodiment. A timing chart showing the operation of data transfer to a microcomputer, Fig. 4 is a block diagram showing the bottom of a computer system using a conventional microcomputer, and Fig. 5 shows a host microcomputer with a bus interface function in this conventional example. FIG. 6 is a timing chart showing the operation of data transfer from the slave microcomputer to the host microcomputer using the bus interface function in this conventional example. 1...Host microcomputer (external package W), 2
...Slave microcomputer (microcomputer), 3...Bus interface, 9...Ready (No. 8, 10...1 pulse ready signal generation circuit

Claims (1)

[Claims] A read signal that controls the operation of an external device to receive data, a write signal that controls the operation of the external device to transmit data, and a ready signal that requests the external device to perform a data reception/transmission operation are used to transmit data. In a microcomputer having a bus interface that performs transfer, when the ready signal is generated and indicates that the external device is ready to receive data, and when the external device is ready to send data. A microcomputer comprising a one-pulse ready signal generation circuit that generates the ready signal as a one-pulse signal.