KR100460994B1 - High-bandwidth I/O device with direct memory access and method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadband input / output device having a direct memory access (DMA) function and a method thereof, wherein a DMA command for transmitting and receiving data between computer systems through a network connection is input from an internal microcontroller unit (MCU). After receiving it, it is temporarily stored in the first-in first-out (FIFO) memory, and the data corresponding to the DMA instruction stored in this first-in-first-out memory is monitored in the temporary data storage memory to prepare the data in the temporary data storage memory. When it is confirmed that the data is transmitted directly to the memory of the computer system to which it belongs, it is to perform the data transmission and reception between the computer system and the other computer system of its own through the network connection network,

As a result, the DMA processing can be made in order, and the data processing time delay of the computer system can be prevented and the CPU can be efficiently used, thereby improving the overall performance of the computer system.

Description

High-bandwidth I / O device with direct memory access function and method thereof

The present invention is a computer system having a general bus structure such as PCI, the device used for broadband input and output, such as InfiniBand, Gigabit-Ethernet, in particular embedded processor embedded in the device When developing a device in the form of a system, the present invention relates to a wideband I / O device used for wideband data transmission and reception between computer systems through a network connection network, and more particularly, to a wideband input / output device having a direct memory access (DMA) function. An apparatus and a method thereof are provided.

In a typical computer system, when a central processing unit (CPU) performs a separate operation without controlling a memory, a broadband input / output device and other peripheral devices that control data transmission and reception with another computer system through a network connection network. It is designed to improve the performance of computer systems by allowing the DMA controller to manage the system bus instead of the CPU so that they can send and receive data directly to and from memory. In a computer system with such a DMA controller is becoming a necessity.

In addition, in a computer system having a PCI bus structure, broadband input / output devices or other peripheral devices may have a role of a DMA controller inside the device when the input / output device has a large amount of input / output.

1 is a block diagram showing a conventional computer system having a DMA controller, which controls data transmission and reception with a CPU 10, a memory 20 divided into a plurality of memory areas 1 to n, and other computer systems. The broadband input / output device 30 and the plurality of peripheral devices 40 to 42 are directly connected to the memory 20 through the broadband input / output device 30, the plurality of peripheral devices 40 to 42, and the system bus 60. And a DMA controller 50 for controlling data transmission and reception.

In FIG. 1, when there is no DMA controller inside the broadband input / output device 50 and the peripheral devices 40 to 42, the authority of managing the system bus 60 from the CPU 10 through the system bus 60 is controlled. The broadband input / output device 50 performs DMA transfer between the computer system to which it belongs and another computer system by the DMA controller 50, and the peripheral devices 40 to 42 directly transmit data to the memory 20. Instruct the transmission.

In this case, the DMA controller 50 compensates the difference in clock speed between the memory 20, the wideband input / output device 30, and the peripheral devices 40 to 42 by using a buffer or the like. have.

In FIG. 1, when a DMA controller exists inside the wideband input / output device 30, the wideband input / output device 30 directly connects the system bus 60 from the CPU 10 via the system bus 60. The entitlement authority is directly accessed to the memory 20 to perform a DMA transfer between the computer system to which it belongs and another computer system.

Even in this case, the DMA controller inside the wideband input / output device 30 should include a device such as a buffer to compensate for the difference in clock speed between the memory 20 and the wideband input / output device 30.

In the conventional computer system as described above, when the broadband input / output device 30 requests data of various memory areas of the memory 20 collectively, DMA transfers are required as many as the corresponding memory areas. Not only 60, but also the wideband input / output device 30 has a disadvantage of waiting at the same time.

In addition, when the data format required by the wideband input / output device 30 and the data format provided by the system bus 60 are different from each other, a data format conversion must be performed whenever a DMA transfer occurs. If there is a difference in clock speed between the wideband input / output device 30 and the system bus 60, it is difficult to predict the amount of buffer for clock conversion.

In addition, since the conventional DMA controller 50 uses the method of instructing the DMA transfer to be defined in the system bus 60, there is a high risk of time delay.

Accordingly, an object of the present invention is to overcome the above-described problems, and an object of the present invention is to receive a DMA command for data transmission and reception between computer systems through a network connection network from an internal micro controller unit (MCU). Is it temporarily stored in FIFO (First-In-First-Out) memory, and is the data corresponding to the DMA instruction stored in this FIFO (hereinafter referred to as FIFO) ready in the temporary data storage memory? If it is confirmed that the data is prepared in the temporary data storage memory, it is possible to directly access the memory of the computer system to which it belongs, and to perform data transmission and reception between the computer system of the member and another computer system through the network connection network. Broadband I / O device with memory access function and its There is provided a method.

A wideband input / output device having a direct memory access function for achieving the object of the present invention comprises: a data reception processor for receiving DMA commands and input / output request data for data input / output from another computer system connected through a network connection network; Receive and analyze the received DMA command of the data receiving processor through the internal bus to specify the DMA processing order, divide the input / output request data into new size data, give the separated data ID, and then input the request data with ID. An internal MCU for newly generating a DMA processing instruction by specifying a memory area address to which data are to be stored or a memory area address from which output request data assigned with ID is read; An internal bus interface for receiving the DMA processing command through an internal bus and storing the DMA processing command in order in a DMA command FIFO; After confirming that the input request data indicated by the DMA processing instruction can be stored in the received data FIFO by referring to the contents of the DMA processing instructions sequentially stored in the DMA command FIFO, the received data FIFO is inputted to the received request data received by the data receiving processor. Store the input request data storage result in the DMA processing result FIFO, check whether the output request data indicated by the DMA processing instruction can be stored in the transmission data FIFO, and store the result in the DMA processing result FIFO. A DMA master controller that determines whether output request data is stored in the transmission data FIFO and outputs an output request data transmission command if output request data is stored; Check the contents stored in the FIFO as a result of DMA processing, and read the input request data stored in the received data FIFO and store them in the corresponding memory area through the system bus, or read the output request data from the memory area through the system bus and transmit the data. An external bus interface for storing in a FIFO; And a data transmission processor for transmitting output request data stored in the transmission data FIFO from another computer system connected through a network connection network when an output request data transmission command of the DMA master controller is input.

In order to achieve the object of the present invention, a direct memory access method of a broadband input / output device includes: receiving, by a data reception processor, DMA commands and data for input / output request data from another computer system connected through a network connection network; An internal MCU analyzing the DMA command to generate a new DMA processing command; An internal bus interface sequentially storing the DMA processing instructions in a DMA instruction FIFO; After confirming that the DMA main controller can store the input request data indicated by the DMA processing instruction in the received data FIFO by referring to the contents of the DMA processing instruction, the data receiving processor stores the input request data received in the received data FIFO. Storing the input request data storage result in a DMA processing result FIFO; Checking whether a DMA main controller can store the output request data indicated by the DMA processing instruction in the transmission data FIFO by referring to the contents of the DMA processing instruction and storing the result in the DMA processing result FIFO; Checking, by the external bus interface, the contents stored in the DMA processing result FIFO, reading input request data stored in the received data FIFO, and storing the input request data in a corresponding memory area through a system bus; Identifying, by an external bus interface, the contents stored in the DMA processing result FIFO, reading the output request data from the corresponding memory area via a system bus, and storing the output request data in the transmission data FIFO; Determining, by a DMA main controller, whether output request data is stored in the transmission data FIFO; Outputting, by a DMA main controller, an output request data transmission command to a data transmission processor if output request data is stored in the transmission data FIFO; And a data transmission processor transmitting output request data stored in the transmission data FIFO from another computer system connected via a network connection network by an output request data transmission command of the DMA main controller.

1 is a block diagram showing a conventional computer system having a DMA controller;

2 is a block diagram illustrating a wideband input / output device having a DMA function according to the present invention;

3 is a block diagram illustrating a DMA command structure according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: CPU 20: Memory

30: wideband I / O devices 40, 41, 42: peripheral devices

50: DMA controller 60: system bus

100: CPU 200: Memory

300: System Bus 400: Broadband I / O Device

410: data receiving processor 420: internal MCU

430: internal bus 440: internal bus interface

450: DMA instruction FIFO 460: DMA master controller

470: Received data FIFO 480: DMA processing result FIFO

490: transmit data FIFO 491: external bus interface

492: Data Send Processor

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, the broadband input / output device 400 having a DMA function according to the present invention includes a memory 200 which is manufactured in a single chip form and is divided into a CPU 100 and a plurality of memory areas 1 to n. It is included in the computer system, and directly access the memory 200 through the system bus 300 for data transmission and reception with other computer system through a network connection network (not shown).

The data receiving processor 410 receives DMA commands and input / output request data for data input / output from another computer system connected through a network connection network.

The internal MCU 420 analyzes the DMA command received by the data receiving processor 410 through the internal bus 430 to specify the DMA processing order, and if there is input / output request data, the input / output request data has a new size of data. After creating a new DMA processing instruction by assigning the ID of the separated data by specifying the memory area address, the memory area address where ID input data is to be stored or the memory area address where ID output data is to be read. do.

As shown in FIG. 3, the DMA processing instruction has a structure indicating the DMA processing order and the ID and the memory area address. As a result, the I / O request data can be distinguished as many as the number of IDs, and the same ID can be identified. The data contained therein can also be collectively processed for the memory areas 1 to n divided by the number that can be displayed in the DMA processing order field.

The internal bus interface 440 receives the DMA processing command through the internal bus 430 and stores the DMA processing command in the DMA command FIFO 450 in order.

The DMA command FIFO 450 preferably sets the depth to n so as to store each DMA processing command for input / output request data including n memory areas.

The DMA master controller 460 refers to the contents of the DMA processing instructions stored in the DMA command FIFO 450 in order to confirm that the input request data indicated by the DMA processing instruction can be stored in the received data FIFO 470. The data reception processor 410 stores the received input request data in the received data FIFO 470 and stores the input request data storage result in the DMA processing result FIFO 480.

The DMA master controller 460 refers to the contents of the DMA processing instructions stored in the DMA command FIFO 450 in order to check whether the output request data indicated by the DMA processing instruction can be stored in the transmission data FIFO 490. After the result is stored in the DMA processing result FIFO 480, it is determined whether output request data is stored in the transmission data FIFO 490. If output request data is stored, an output request data transmission command is executed. 492).

The external bus interface 491 checks the contents stored in the FIFO 480 as a result of the DMA processing, reads input request data stored in the received data FIFO 470, and stores the corresponding memory area 1 through n through the system bus 300. The output request data is read from the memory areas 1 to n through the system bus 300 and stored in the transmission data FIFO 490.

The external bus interface 491 stores a system bus 300 clock and a wideband input / output device of a computer system when the input request data is stored in the memory areas 1 to n or the output request data is read from the memory areas 1 to n. The input / output request data transmission / reception clocks are converted to automatically compensate for the difference between the clocks of the internal bus 430 of 400.

The data transmission processor 492 transmits the output request data stored in the transmission data FIFO 490 from another computer system connected through a network connection network when the output request data transmission command of the DMA master controller 460 is input.

The broadband input / output device having a direct memory access function according to the present invention configured as described above operates as follows.

When a data input / output request is input to a computer system including the broadband input / output device 400 according to the present invention from another computer system connected through a network connection network, the data receiving processor 410 receives DMA command and input / output request data for data input / output. After receiving from the other computer system, the DMA command is transmitted to the internal MCU 420 through the internal bus 430.

Accordingly, the internal MCU 420 analyzes the DMA command received from the data receiving processor 410 to generate a new DMA processing command.

At this time, the internal MCU 420 analyzes the DMA command to designate a DMA processing order, divides the input / output request data into data of a new size, assigns an ID of the separated data, and then inputs request data to which the ID is assigned. By specifying a memory area address to be stored or a memory area address to read output request data given with ID, a new DMA processing command is generated and transmitted to the internal bus interface 440. The DMA processing command is illustrated in FIG. As described above, a structure indicating the DMA processing order and the ID and memory area address is generated.

In addition, when the DMA processing instruction having a structure indicating the DMA processing order and ID and memory area address is transmitted to the internal bus interface 440 by the internal MCU 420, the internal bus interface 440 may execute the DMA processing instruction. Are stored in order in the DMA command FIFO 450.

After the DMA processing instructions are sequentially stored in the DMA command FIFO 450 as described above, the DMA master controller 460 instructs the received data FIFO 470 in the DMA processing command by referring to the contents of the DMA processing command. After confirming that the input request data can be stored, if it is confirmed that the data can be stored, the data reception processor 410 stores the received input request data in the received data FIFO 470, and stores the input request data storage result as a result of DMA processing. Store in FIFO 480.

Subsequently, the DMA master controller 460 checks whether the output request data indicated by the DMA processing instruction can be stored in the transmission data FIFO 490 by referring to the contents of the DMA processing instruction, and if it is confirmed that the data can be stored, the result Is stored in the DMA processing result FIFO 480.

After the input request data storage result and the output request data storage state result are stored in the DMA processing result FIFO 480 as described above, the external bus interface 491 checks the contents stored in the DMA processing result FIFO 480. The input request data stored in the received data FIFO 470 is read and stored in the memory areas 1 to n of the memory 200 through the system bus 300.

The external bus interface 491 also checks the contents stored in the FIFO 480 as a result of the DMA processing, and reads the output request data from the corresponding memory areas 1 to n of the memory 200 through the system bus 300. The transmission data is stored in the FIFO 490.

In this case, the DMA master controller 460 determines whether the output request data is stored in the transmission data FIFO 490. If the output request data is stored in the transmission data FIFO 490, the DMA main controller 460 sends the data to the data transmission processor 492. An output request data transmission command is output, whereby the data transmission processor 492 transmits output request data stored in the transmission data FIFO 490 from another computer system connected through a network connection network.

As described above, the broadband I / O device having the direct memory access function according to the present invention allows the internal MCU to determine the processing order of the DMA of the DMA main controller managing the transmit / receive data FIFO, the DMA command FIFO, and the DMA processing result FIFO. This eliminates the need for a separate DMA processing order determining circuit, and allows DMA processing to be consistent in the order in which it is stored in the DMA command FIFO.

In the broadband I / O device having the direct memory access function according to the present invention, since the external bus interface automatically converts the I / O request data transmission / reception clock to compensate for the clock difference between the clock of the computer system and the broadband I / O device, the internal MCU for this is And since the operation of the CPU of the computer system is not necessary, it is possible to prevent the data processing time delay and improve the overall performance.

In the broadband input / output device having the direct memory access function according to the present invention, since the DAM instruction structure can process the transmit / receive data composed of several memory areas, the DMA order is determined for each memory area. Since it does not require complicated operations, the CPU of the internal MCU and the computer system can be efficiently used.

What has been described above is only one embodiment for implementing a broadband input / output device having a direct memory access function and a method thereof according to the present invention, and the present invention is not limited to the above-described embodiment, and the claims Without departing from the gist of the present invention claimed in the scope, anyone of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (6)

A data receiving processor for receiving DMA commands and input / output request data for data input / output from another computer system connected through a network connection network; Receive and analyze the received DMA command of the data receiving processor through the internal bus to specify the DMA processing order, divide the input / output request data into new size data, give the separated data ID, and then input the request data with ID. An internal MCU for newly generating a DMA processing instruction by specifying a memory area address to which data are to be stored or a memory area address to read output request data to which an ID is assigned; An internal bus interface for receiving the DMA processing command through an internal bus and storing the DMA processing command in order in a DMA command FIFO; After confirming that the input request data indicated by the DMA processing instruction can be stored in the received data FIFO by referring to the contents of the DMA processing instructions sequentially stored in the DMA command FIFO, the received data FIFO is inputted to the received request data received by the data receiving processor. Store the input request data storage result in the DMA processing result FIFO, check whether the output request data indicated by the DMA processing instruction can be stored in the transmission data FIFO, and store the result in the DMA processing result FIFO. A DMA master controller that determines whether output request data is stored in the transmission data FIFO and outputs an output request data transmission command if output request data is stored; Check the contents stored in the FIFO as a result of DMA processing, and read the input request data stored in the received data FIFO and store them in the corresponding memory area through the system bus, or read the output request data from the memory area through the system bus and transmit the data. An external bus interface for storing in a FIFO; And A data transmission processor for transmitting output request data stored in the transmission data FIFO from another computer system connected through a network connection network when an output request data transmission command of the DMA main controller is inputted. Broadband input and output device with a direct memory access function, characterized in that consisting of. The method of claim 1, wherein the internal MCU is A broadband input / output device having a direct memory access function, characterized by generating a DMA processing instruction in a structure representing a DMA processing sequence and an ID and a memory area address. The method of claim 1, wherein the DMA command FIFO is and a depth thereof is set to n so that each DMA processing instruction for input / output request data consisting of n memory areas can be stored. The system of claim 1, wherein the external bus interface is When the input request data is stored in the memory area or the output request data is read from the memory area, the input / output request data transmission / reception clocks are converted to automatically compensate for the difference between the system bus clock of the computer system and the internal bus clock of the wideband I / O device. A wideband input / output device having a direct memory access function. Receiving, by a data receiving processor, DMA commands for inputting / outputting data and input / output request data from another computer system connected through a network; An internal MCU analyzing the DMA command to generate a new DMA processing command; An internal bus interface sequentially storing the DMA processing instructions in a DMA instruction FIFO; After confirming that the DMA main controller can store the input request data indicated by the DMA processing instruction in the received data FIFO by referring to the contents of the DMA processing instruction, the data receiving processor stores the input request data received in the received data FIFO. Storing the input request data storage result in a DMA processing result FIFO; Checking whether a DMA main controller can store the output request data indicated by the DMA processing instruction in the transmission data FIFO by referring to the contents of the DMA processing instruction and storing the result in the DMA processing result FIFO; Checking, by the external bus interface, the contents stored in the DMA processing result FIFO, reading input request data stored in the received data FIFO, and storing the input request data in a corresponding memory area through a system bus; Identifying, by an external bus interface, the contents stored in the DMA processing result FIFO, reading the output request data from the corresponding memory area via a system bus, and storing the output request data in the transmission data FIFO; Determining, by a DMA main controller, whether output request data is stored in the transmission data FIFO; Outputting, by a DMA main controller, an output request data transmission command to a data transmission processor if output request data is stored in the transmission data FIFO; And Transmitting, by a data transmission processor, output request data stored in the transmission data FIFO from another computer system connected via a network connection network by an output request data transmission command of the DMA master controller; Direct memory access method of a wideband input / output device, characterized in that consisting of. The method of claim 5, wherein the internal MCU analyzes the DMA command to generate a new DMA processing command. Receive and analyze the received DMA command of the data receiving processor through the internal bus to specify the DMA processing order, divide the input / output request data into new size data, give the separated data ID, and then input the request data with ID. Direct memory access method of a wideband input / output device, characterized in that a new DMA processing instruction is generated by specifying a memory area address to which data is stored or a memory area address from which output request data given an ID is read.