JPH05158838A - Semiconductor device for controlling communication - Google Patents

Abstract

PURPOSE:To execute the efficient transmission and reception of data by detecting the end of reception by a host device even in the case that received data is directly transferred to a memory without intermediary of the host device, in a communication controlling semiconductor device to be used in an information processor. CONSTITUTION:A serial/parallel conversion circuit 1 to convert a pulse signal received through an input terminal 8 into parallel data and a buffer register 2 to hold once the parallel-converted parallel data are provided. Besides, a host interface circuit 3 to interface with the host device and a comparator circuit 10 for comparing the received data with optional specified data are provided. Further, a register 9 to store the optional specified data and a pulse generation circuit and a control signal line to inform the outside of coincidence when the received data and the optional specified data coincide with each other are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for communication control used in an information processing device, and more particularly to transmitting and receiving data by an asynchronous method and receiving data by a direct memory access method without passing through a host device. The present invention relates to a communication control semiconductor device for sending to a memory.

[0002]

2. Description of the Related Art FIG. 2 shows an overall block diagram of a conventional example of a communication control semiconductor device.

A serial-parallel converter circuit 1 for converting a pulse signal received through an input terminal 8 into parallel data, a buffer register 2 for temporarily holding parallel-converted parallel data, and a host device for interfacing with a host device. It has an interface circuit 3.

Further, it has control signal lines for transmitting the direct memory access request signal 4, the direct memory access permission signal 5, and the data read signal 6, respectively.

Next, the actual operation will be described.

The received signal pulse input from the input terminal 8 is converted into parallel data by the serial-parallel conversion circuit 1 and temporarily held in the buffer register 2.

When the data is input to the buffer register 2, the upper interface circuit 3 indicates that the data has been received by the direct memory access request signal 4,
Notify the direct memory accelerator controller.

When the direct memory access permission signal 5 is returned from the direct memory access controller, the received data is output to the outside in synchronization with the data read signal 6 through the data bus 7.

[0009]

In the conventional semiconductor device for communication control, the received data is directly transmitted without passing through the host device.
When transferring data to a higher-level device using direct memory access control that transfers data to the memory, unless the data length is set in advance, when the data transfer ends,
There was a drawback that the higher-level device did not know at all.

Further, since the data length is fixed, extra data must be transmitted / received until the predetermined data length is reached even if the actually transmitted / received data length is short, resulting in poor data transfer efficiency. There was a drawback.

An object of the present invention is to transfer the received data directly to the memory without passing through the host device, and even if the length of the received data is not set in advance, the host device recognizes the end of reception, and as a result, the data is received. It is an object of the present invention to provide a semiconductor device for communication control capable of efficiently transmitting and receiving data because the length can be freely selected.

[0012]

A semiconductor device for communication control used in an information processing apparatus of the present invention comprises a serial-parallel conversion circuit for converting a pulse signal received through an input terminal into parallel data, and parallel-converted parallel data. Is temporarily held, a host device interface circuit for interfacing with a host device, a comparator circuit for comparing received data with arbitrary data specified in the protocol, and a protocol specified in the protocol If the register that stores arbitrary data, the received data, and the arbitrary data defined in the protocol match, the pulse generator that notifies the external match, direct memory access request signal, direct memory access Equipped with control signal line for transmitting permission signal and data read signal There.

[0013]

The pulse train of the received data is taken into the serial-parallel conversion circuit through the input terminal and converted into parallel byte data. The comparator circuit, which compares the received data with the specific data preset in the comparison data register, outputs a data coincidence detection signal to the higher-level device if the comparison result shows that the both data are the same. As a result, the host device recognizes the end of reception and eliminates the reception of extra dummy data as in the prior art.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The pulse train of the received data is taken into the serial-parallel conversion circuit 1 through the input terminal 8 in synchronization with the system clock of this semiconductor device.

The captured pulse train is converted by the serial-parallel conversion circuit 1 from serial data to parallel data, for example, 8-bit byte data.

In the case of converting serial bit data to parallel bit data, it is assumed that the bit length of the parallel bit data is preset in the semiconductor device after the power is turned on and before the use is started.

When the conversion is completed in the serial-parallel conversion circuit 1, the received data is once transferred to the buffer register 2. If the data is not transferred to the buffer register, the next pulse train will be overwritten with the data on the serial-parallel conversion circuit, and the correct data cannot be transferred to the host device.

When the comparator circuit 10 detects that the buffer register 2 stores the data converted by the serial-parallel conversion circuit, the comparator circuit 10 compares the data with the arbitrary data defined in the protocol preset in the comparison data register 9. When the data is compared and the data is the same, the data coincidence detection signal is output to the host device through the signal line 11 in synchronization with the read signal 6.

If they are not the same data, the data coincidence detection signal is not output.

The comparison data register 9 is provided with a power source O.
It is assumed that after N, before the start of using the present semiconductor device, comparison data having an arbitrary data bit string length defined in the protocol has been set in advance.

What can be set in the comparison data register 9 is
Although it is an arbitrary data bit string, it is assumed that data having a length equal to or larger than the bit string of the parallel data after the serial-parallel conversion is not set.

Further, in order to distinguish it from the received data, a specific control code not included in the received data may be set beforehand.

This semiconductor device has a comparator circuit 10
At the same time as performing the comparison operation, when the upper interface circuit 3 detects that the received data is transferred from the serial-parallel conversion circuit 1 to the buffer register 2, the direct memory access request signal 4 prepares for the transfer of the received data. This is notified to the external direct memory access controller.

The direct memory access controller mentioned here is a general term for a semiconductor device for controlling so that the received data can be directly transferred at high speed between the semiconductor device and the memory without passing through the host device.

In this semiconductor device, when the direct memory access controller detects that the direct memory access request signal 4 is returned to the direct memory access request signal 4, the semiconductor memory synchronizes with the data read signal and stores it in the buffer register 2. The received data is output to the outside through the data bus 7.

The output data is directly written into the memory by the direct memory access controller without passing through the host device.

At this time, as described above, when the reception data is output to the outside, if the comparison data and the reception data match, the detection signal is also output to the outside through the signal line 11 at the same time.

The host device receives the detection signal and can know that the same data as the preset arbitrary data set in the protocol has been received.

In other words, this means that all data reception until the reception of the same data is completed.

[0032]

As described above, according to the present invention, by adding a comparison circuit for comparing the received data and the arbitrary data defined in the protocol, the received data can be transmitted by the direct memory access method without passing through the host device. Even when the data is directly transferred to the memory, the end of reception can be detected by the host device even if the length of the received data is not predetermined and the length is arbitrary.

Therefore, as compared with the conventional method in which the data length to be received must be determined in advance, the data length can be freely selected, so that there is an effect that efficient data transmission / reception can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional technique.

[Explanation of symbols]

 1 Silipara conversion circuit 2 Buffer register 3 Upper interface circuit 4 Direct memory access request signal 5 Direct memory access permission signal 6 Data read signal 7 Data bus 8 Input terminal 9 Comparison data register 10 Comparator circuit 11 Output terminal

Claims (1)

[Claims] 1. A semiconductor device for communication control, which is used in an information processing device and transmits and receives in an asynchronous method, comprising: a serial-parallel conversion circuit for converting a pulse signal received through an input terminal into parallel data; and a parallel conversion circuit. Buffer register that temporarily holds the parallel data, the host device interface circuit that interfaces with the host device, the comparator circuit that compares the received data with the arbitrary data specified in the protocol, and the protocol When the register that stores the specified arbitrary data, the received data, and the arbitrary data specified by the protocol match, the pulse generation circuit that notifies the external match, the direct memory access request signal, Direct memory access permission signal and data read signal are transmitted Communication control semiconductor device and a control signal line.