JPS62269539A - Communication controller - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU by providing a termination detection circuit counting and detecting a bit string representing the absence of reception signal data transmission and applying DMA transfer to asynchronous serial reception data to a memory. CONSTITUTION:A communication control LSI1 receives asynchronizing reception data from a data terminal equipment and the data is subjected to DMA transfer to a memory 4 by the control of a DMA controller 7 for each character. When the reception packet is finished, the reception signal goes to a high state. The termination detection circuit 6 detects the high state, counts the reception clock during the said high state and when the count reaches a preset number, an interruption signal is generated for an interruption controller 3. Since hardware detects the end of packet and generates the interruption signal in this way, it is not required to transfer a data through a CPU 2, the DAM transfer is used and the load of the CPU 2 is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication control device for receiving asynchronous serially transmitted data from a data terminal device in data communication equipment.

BACKGROUND ART FIG. 3 shows the configuration of a conventional communication control device 10. In FIG. 3, reference numeral 1 denotes a communication control LSI that converts serially received data from a data terminal device into parallel data and sends it to the CPU bus 5.

2 is a CPU that controls this system. 3 is an interrupt controller that receives an interrupt signal from the communication control LSII and causes the CPU 2 to generate an interrupt. 4 is a memory for buffering data received by this system from a data terminal device.

Conventionally, when receiving asynchronous data in a communication control device such as the one described above, data transfer from the communication control LSII is read character by character by the CPU 2 and written to the memory 4. Further, the end of a received packet is detected by not generating an interrupt indicating that the next character has been received by the communication control LS 11 within a certain period of time.

Problems to be Solved by the Invention However, in the conventional communication control device 10 described above, direct memory access (hereinafter abbreviated as DMA) cannot be used for data transfer from the communication control LSI 1 to the memory 4; It must be made. Therefore, there is a problem in that many steps of the CPU 2 are used for data transfer, resulting in a heavy load on the CPU 2.

The present invention solves these conventional problems, and aims to provide a communication control device that enables DMA transfer by detecting the end of a received packet through hardware processing. It is.

Means for Solving the Problems In order to achieve the above object, the present invention provides a termination detection circuit that detects and counts bit strings indicating that no data transmission is being performed in a received signal, and the present invention provides a termination detection circuit that detects and counts bit strings indicating that data transmission is not performed in a received signal. , it is possible to detect the end of a packet.

According to the present invention, the load on the CPU can be reduced by performing DMA transfer of asynchronous serial reception data to the memory.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, 6 is a termination detection circuit consisting of a counter, a gate circuit, etc. for detecting the termination of received data; 7
1 is a DMA controller, 10a is the entire communication control device, and other symbols similar to those in FIG. 3 represent the same names.

Next, the operation of the above embodiment will be explained with reference to FIG. Communication control LSI 1 receives asynchronous reception data from a data terminal device, and performs DMA for each character.
DMA transfer is performed to the memory 4 under the control of the controller 7.

When the received packet ends, the received signal goes high. The termination detection circuit 6 detects this state, counts the reception clocks during the high state, and generates an interrupt signal to the interrupt controller 3 when the number reaches a predetermined number. That is, in FIG. 2, the high state indicating the end of the reception signal a is detected at (a), and counting of the reception clock b is started. If the received signal continues to be in a high state until a predetermined number of clocks are counted, the termination detection circuit 6 outputs an interrupt signal c.
ffo). If the reception signal becomes low by the time a pre-specified number of clocks are counted, that is, if the start bit of the next character is received, it is determined that the packet has not ended and reception continues.
The termination detection circuit 6 is reset.

According to the above embodiment, since the end of the packet is detected by hardware and an interrupt signal is generated, data transfer is performed by the CPU.
2, DMA transfer can be used and the load on the CPU 2 can be reduced.

As described in detail, according to the present invention, the level of the received data becomes constant as the end of the asynchronous received packet coincides with the end of the received data. Since the interrupt signal is generated by hardware after waiting for the elapsed time, data can be transferred by DMA without going through the CPU, which has the advantage of reducing the load on the CPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a communication control device according to an embodiment of the present invention, FIG. 2 is a timing chart of the same, and FIG. 3 is a block diagram of a conventional communication control device. 1... Communication control LSI, 2... CPU, 3...
Interrupt controller, 4... Memory, 5... CPU bus, 6... Termination detection circuit, 7... DMA controller, 10a... Communication control device.

Claims (1)

[Claims] A communication control LSI that receives asynchronous serial reception data from a data terminal device, converts it into parallel data, and sends it out on a CPU bus, and a CPU and memory connected via the CPU bus, and direct memory access. A controller, and a termination detection circuit that measures a continuation clock of a level change accompanying the termination of the received data, and generates an interrupt signal as if the received data has terminated when the continuation time has elapsed for a certain period of time. , a communication control device that performs direct memory access between the communication control LSI and the memory.