JPH04117841A - Communication speed detection method in start-stop synchronizing communication system - Google Patents

Abstract

PURPOSE:To realize the detection of a communication speed rich in the economy and flexibility by utilizing the synchronizing communication operating mode so as to receive the synchronizing mode sampling a character and using timing information of a data signal line as a basic data for detecting the speed. CONSTITUTION:A communication control circuit LSI 11 has the synchronizing communication operating mode in addition to the start-stop communication operating mode. In the case of receiving a start-stop communication character from a data signal line, a CPU 14 sets the operating mode of the LSI 11 to the synchronizing communication operating mode, a speed changeover circuit 12 outputs a data sampling clock whose speed is over the communication speed and a synchronizing establish signal output circuit 13 outputs a level signal representing the synchronization establishment to the LSI 11, and the LSI 11 uses the clock signal so as to implement the synchronization mode reception in which the signal waveform of the character is sampled, and the CPU 14 detects the transmission speed of the received character in response to the timing information on the data signal line obtained from the result of the sampling of the character recognized as the reception data and sets the LSI 11 to the start-stop communication mode at the detected communication speed again.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an asynchronous communication system that communicates communication data in an asynchronous manner, and particularly to communication speed detection of an asynchronous communication system that detects the communication speed of communication data. Regarding the method.

(Prior art) Conventionally, in this type of communication speed detection method, a plurality of receiving circuits are arranged in parallel and are set to perform reception at the respective communication speeds to be detected, and when a character is received, Another type of communication system detects the communication speed by receiving characters using the plurality of receiving circuits and determining whether the receiving circuits have correctly received the data.

In addition, when a character is received, the period during which the received data signal line is at a low level or low level is automatically measured using a counter or other means, and after the character reception is completed, the communication speed is detected from the measurement result. There was something to do. This method assumes that only one character is counted at any communication speed, but since the communication speed is unknown, the end of character reception is the time equivalent to the transmission time of one character at the lowest speed to be detected. The decision was made based on the fact that the period had passed.

(Problem to be Solved by the Invention) However, in the method of arranging multiple receiving circuits in series, the type of speed that can be detected is determined at the time of designing the receiving circuit to be installed, and changes are easy. isn't it. Further, since receiving circuits for only the types of speeds to be detected are required, it is not economical, and furthermore, since it is necessary to determine the characters to be detected in advance, there is a problem that the types of characters to be detected are limited.

In addition, in the method of measuring the level of the signal line, the end of character reception is determined when the time equivalent to the transmission time of l character at the minimum speed to be detected has elapsed, so the actual communication speed is lower than the minimum speed. No matter how fast the speed is, multiple characters cannot be received within the same time period, and as a result, the character reception interval is limited to no more than one character reception at the lowest speed.

For example, if the minimum speed to be detected is 50 [bps], the character length is 8 hits, and there are start and stop hits of 1 bit each before and after the character length,
The character reception interval is 1150X (8+
Program-based control, which requires 1+1) 115 (sec)/200 (msec) or more, has the problem that special measures such as insertion of a delay loop (diley 1 loop) are required. Additionally, since hardware such as a counter that measures time must be provided separately from the communication control means, the number of components increases and This has led to serious problems such as increased production costs and increased mounting space.

The present invention was made in view of the above problems, and allows the use of a synchronous communication operation mote with a small amount of additional hardware, without increasing the number of parts even if there are many types of speeds to be detected. To provide a communication speed detection method for an asynchronous communication system capable of detecting the communication speed of a character without taking up storage space, and capable of performing speed detection with excellent economical efficiency and great flexibility. With the goal.

(Means for Solving the Problems) In the present invention, via a predetermined communication target and a data signal line,
In an asynchronous communication system that performs data communication at multiple communication speeds, the central It has a communication control means having a function of performing data communication by switching by a processing unit, and when receiving an asynchronous communication character from the data signal line, the central processing unit or the communication control means controls the synchronous communication. The signal waveform of the character is sampled and linked using the clock signal of at least the communication speed to be detected. The transmission speed of the received character is detected in accordance with the timing information of the data signal line, and the communication control means is reset to the asynchronous communication operation mode of the detected communication speed.

(Function) Synchronous mode reception that samples and links characters by using the synchronous communication operation mode that receives data using an external input clock, which is included in most communication control means such as general communication control LSIs. The timing information of the data signal line obtained from the results is used as the basic data for speed detection.

Therefore, in the present invention, by using a synchronous communication operation mote, it is possible to sample and link data signal lines with only a small amount of additional hardware, and the timing information obtained by this sampling method can be used to detect speed. This enables economical and flexible communication speed detection.

(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a block diagram showing a schematic configuration of an asynchronous data communication device using a communication speed detection method according to the present invention. In the figure, a communication control circuit (rLs IJ
That's what it means. ) 11 is a small, high-performance LSI for communication control. When designing such LSIs, microprocessor-controlled communication devices called serial communication controllers or multiprotocol communication controllers are often used, and most of these devices process data using clock signals input from outside. It has a synchronous communication operation mode for receiving data. The LSI 11 of the present invention also includes a synchronous communication operation mote that receives data in synchronization with a clock signal input from the communication speed switching circuit 12, in addition to an asynchronous communication operation mote, which will be described later. central processing unit (r
cPU". ) 14, the asynchronous communication operation mode or synchronous communication operation mode is set, and data communication is performed with a predetermined communication target via the transmission data signal line 21 and the reception data signal line 22, and the interrupt An interrupt signal is output to the CPU 4 via the signal line 24. Note that if the set mode is a synchronous communication operation mode, it is assumed that synchronization has been established based on the level signal output from the synchronization establishment signal output circuit 13.
A receiving operation can be performed in which the received data signal line level is sampled and linked using the clock signal output from the speed switching circuit 12.

The speed switching circuit 12 switches the clock signal of an arbitrary communication speed from among the clock signals of different communication speeds that can be outputted according to the control of the CPU 14, and selects the switched clock signal as (2).

It is output to 5ill. That is, speed switching circuit 1
2 outputs a clock signal four times faster than a predetermined maximum communication speed of the character to be detected, for example.

The synchronization establishment signal output circuit 13 outputs a level signal indicating establishment of synchronization to the LSI 11 under the control of the CPU 14.

C1) U14 connects LSllll,
Communication speed switching circuit 12 and synchronization establishment signal output circuit 13
The operation of L is controlled via the interrupt signal line 24.
S I 1. When an interrupt signal from l is input,
Performs predetermined interrupt processing. That is, the CPU 1.4 has in advance a 1-bit count reference value corresponding to each communication speed built-in, and compares the 1-bit length actual count value detected by the above-mentioned interrupt processing with each of the above-mentioned count reference values. Characters that can be used in the present invention, which detects the communication speed by doing so, are characters that are ASCII and have odd values, and FIG. 2 is a diagram of a communication data character waveform showing one example thereof. Normally, the received data signal line 22 is at a high level, and characters are transmitted in positive logic (logical value 1 or high level) in order from the lower bits, starting with a 1-bit long start bit at a low level. In this example, the character length is 8 bits, and a high level 1-bit long stop bit is added after the character data. The character code in FIG. 2 is ODh in hexadecimal and corresponds to the carriage return (CR,) character of the ASCII code.

Next, the communication speed detection operation in the asynchronous data communication device shown in FIG. 1 will be explained.

When detecting the communication speed, the CPU 1.4 first detects the LS
The LST II is controlled to set the operation mode of the LST II to the synchronous communication operation mode. Then, the speed switching circuit 12 is controlled, and the speed switching circuit 12 outputs a preset data sampling clock (in the embodiment, a clock four times the maximum communication speed of the character to be detected) to the LSTII, and synchronization is established. Controlling the signal output circuit 13 to cause the LSIII to output a level signal indicating establishment of synchronization,
Set to receive execution state.

When the LSIII receives a level signal, it assumes that synchronization has been established, and performs a receiving operation of sampling the level of the received data signal line using the clock signal output from the speed switching circuit 12.

Then, each time the set number of hits (for example, 8 bits shown in Figure 2) is completed, the LSIII
transmits an interrupt signal requesting receipt of the received data received from the received data signal line 22 to the interrupt signal line 24.
It outputs to the CPU 14 via.

Upon receiving the interrupt signal from Lu11, the CPU 14 reads the sample link result of the received data signal line 22 as received data.

Here, if no character has been received yet, the level of the received data signal line 22 is high level, so the data to be read is "F F h", and when the CPU 1.4 takes in the above data, Discard this and wait for the next interrupt request. When the reception of a predetermined character, for example, a character with an odd value in the ASCII code, begins, the level of the reception data signal line 22 becomes low level, and "0" appears in the reception data that the CPUI receives. Bits of level ■ appear consecutively. When the CPU 4 recognizes the received data described in 1., it monitors the subsequent received data, counts how many consecutive "0" level bits there are, and when a "0" level bit appears again in the received data, it returns this value. End the count.

In the embodiment, since the lowest hit of a child character with an odd number of ASCII codes is "BI", the period in which "0" level bits are continuous in the received data is the reception period of the start bit (starting start bit). (1 bit time in synchronous communication). Therefore, 1 bit time corresponding to each communication speed
If a count reference value for bits is stored in the CPU 1.4 in advance, the communication speed can be detected by comparing it with the actual count value.

When the CPU 14 detects the communication speed, the CPU 14 puts the output of the synchronization establishment signal output circuit 13 into a receiving stop state, sets the communication speed to the detected communication speed, and sets the communication speed to the detected communication speed. It is possible to reset l to the asynchronous communication operation mode and start data communication in the asynchronous mode.

Therefore, in this embodiment, in the synchronous communication operation mode, the communication data signal line level is sampled at a speed of - the maximum communication speed of the character to be detected, and the communication speed is detected from the sample link result. According to the detected communication speed, the asynchronous communication operation mote can perform data communication with the communication target, so compared to the conventional asynchronous pig communication device, the speed can be increased without adding much hardware. Detection is possible, and the characters that can be used for speed detection are highly flexible. Furthermore, changes in the speed to be detected can be handled by simply rewriting the 1-minute count reference value table corresponding to the communication speed set in the CPU.

Furthermore, the timing of speed detection is almost always the same as the end of the start bit, and the restrictions on the time interval with subsequent characters can be significantly relaxed.

(Effects of the Invention) As described and described above, the present invention enables normal data communication to be performed in an asynchronous communication system that performs data communication at a plurality of communication speeds with a predetermined communication target via a data signal line. It has a communication control means having a function of performing data communication by switching between a target asynchronous communication operation mode and a synchronous communication operation mode in which data is received using a clock signal of an arbitrary speed, by a central processing unit, When receiving an asynchronous communication character from the data signal line, the central processing unit or the communication control means is set to the synchronous communication operation mode, and the character is detected by the clock signal at least at a communication speed higher than the communication speed to be detected. The transmission speed of the received character is detected according to the timing information of the data signal line obtained from the sample link result of the character recognized as received data, and the transmission speed of the received character is detected. Since the control means is reset to the asynchronous communication mode of the detected communication speed, it is possible to use a synchronous communication mode with the addition of a small amount of hardware, and there are many types of speeds to be detected. It is possible to detect the communication speed of a character without increasing the number of parts or taking up storage space, making it possible to perform speed detection with excellent economic efficiency and great flexibility.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an asynchronous data communication device using a communication speed detection method according to the present invention. FIG. 2 is a diagram showing communication data character waveforms in this embodiment. 11. Communication control circuit (LSI), x2... Communication speed switching circuit, 13. Cycle establishment signal output circuit, ]4. Central processing unit (CPU), 21.22... Data signal line, 23. ...Data bus, 24...Interrupt signal line.

Claims (1)

[Claims] In an asynchronous communication system that performs data communication at multiple communication speeds with a predetermined communication target via a data signal line,
Communication control with a function to perform data communication by switching between an asynchronous communication operation mode for normal data communication and a synchronous communication operation mode for receiving data using a clock signal at an arbitrary speed using the central processing unit. means, when receiving an asynchronous communication character from the data signal line, the central processing unit sets the communication control means to the synchronous communication operation mode, Performing synchronous mode reception in which the signal waveform of the character is sampled using a clock signal, and detecting the transmission speed of the received character according to timing information of the data signal line obtained from the sampling result of the character recognized as received data. ,
A communication speed detection method for an asynchronous communication system, characterized in that the communication control means is reset to the asynchronous communication mode of the detected communication speed.