JPH01246941A - System for controlling communication of computer data - Google Patents

Abstract

PURPOSE:To enable transmission/reception of serial data of a fixed length between multi-processors by adding a circuit which makes beforehand the serial data accumulated in a buffer memory circuit transmittable to each slave equipment. CONSTITUTION:The processor of a master equipment OF0 transmits serial data signals to slave equipments OF1...OFn at every fixed time. The processor of each slave device OF1...OFn receives the serial data by using a data transmission/reception circuit connected to a transmission data line TxD and reception data line RxD. The serial data inputted to the reception data line RxD are converted into parallel data at every 1-byte data at an SP converter circuit and whether or not the address data of the inputted signals coincide with the address data of its own equipments is checked by means of an address coincidence detecting circuit 7. Only when the address data coincide when each other, a reception control circuit 5 is actuated by means of the circuit 7 and the data of input signals are transferred to a received data FIFO circuit 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a computer data communication control system,
In particular, it relates to computer data communication control methods using multiprocessors.

[Prior art] Conventionally, 5DLC was used as a computer data communication control method.
Method (Synchronous Data Line
There are controls shown in FIGS. 2, 3, and 4. In FIG. 2, a computer data device 0Fn (the subscript n indicates an address, n=o indicates a master device, n=1.2...n indicates a slave device).

), the processor of the master device OFO is the fourth
It is connected to the transmission data line Tx6 and the reception data line RxD via the data transmission/reception circuit shown in the figure. Also, slave device O
A plurality of processors F, . . . OFn are connected to the transmission data line TxD in FIG.
Connected to reception data line RxD. Note that slave device O
In F□...OFn, the reception data line RxD shown in FIG.
The transmission data line TxD is read as the transmission data line TxD, and the transmission data line TxD is read as the reception data line RxD. The structure of the communication data starts from the least significant bit LSB as shown in Figure 3, starting with the start flag F.
Gs.

It consists of address data AD, data block DT, and stop flag FGp. The data transmission/reception circuit is
SP conversion circuit for converting serial data into parallel data; PS conversion circuit wr2 for converting parallel data into serial data; reception data buffer circuit 1a for temporarily storing received data; and temporary storage for transmitting data. a data reception detection circuit 7 for detecting the arrival of data, and a reception control circuit 5 activated by the data reception detection circuit at the time of data arrival. An interrupt signal line IS that notifies the processor of the arrival of data, and a transmission control circuit 6. It is composed of a transmission data ready signal line T x S indicating the end of data transmission, and a data bus interface circuit 8 of the processor.

In the computer data communication control method with the above configuration, the second
The processor of the master device oFo in the figure sends the start flag FGs, stop flag FGp, which indicates the start and end of data, to the slave devices OF□...OFn, as shown in FIG. 3, to the slave devices ○F1...OFn. A serial data signal consisting of address data AD and a data block DT of a fixed length is transmitted. Slave device ○F engineering in Figure 3...OFn's processor is the second
The arrival of data is detected by the interrupt signal line IS output from the reception detection circuit 7 of the data transmission/reception circuit in FIG. 4, which is connected to the transmission data line TxD and reception data line RxD in the diagram, and the ongoing processing is immediately interrupted. Then, the interrupt processing program 10 shown in FIG. 5 is executed. First, address data is received from the receive data buffer circuit 1a in FIG.
If the address does not match the preset address of the own device, the interrupt process is terminated via return 18 based on the judgment in judgment box 12. The interrupted program resumes the interrupted process. If the addresses match as determined by the decision box 12, the number of blocks of data to be read next is set in a counting memory in a process 13. Processing 14
．． After transferring the number of bytes set by 15.16 and decision box 17 to the memory area of the own device, the interrupt processing is terminated via return 18. Further, the transmission is performed by program processing at appropriate timing so as not to collide with other slave devices OF□...OFn.

[Problems to be Solved by the Invention] Since the conventional computer data communication control system is configured as described above, in order to transmit serial data of a fixed length from the master device ○ F0 side at once, it is necessary to Since it is necessary to constrain the processors on the device OF, ...OFn side, it is difficult for the processors on the slave device OF1...OFn to process other programs that require time and timing at the same time. There are issues that need to be resolved.

[Means for Solving the Problems] A computer data communication control system according to the present invention includes address matching detection means for detecting whether or not the address of received data is addressed to the local station and outputting a reception flag; Computer data is transmitted and received by a predetermined protocol through the received data storage means that sequentially stores the received data and the transmitted data storage means that sequentially stores the transmitted data by activation, and the received and transmitted data storage means according to the reception flag. [Object of the Invention] This invention was made in order to eliminate the drawbacks of the conventional devices as described above. By adding a circuit to each slave device that enables the transmission of serial data stored on the slave device side, it is possible to send and receive serial data of a fixed length between multiprocessors without going through the processor on the slave device side. The purpose is to provide a communication method that allows

[Embodiment of the Invention] Hereinafter, an embodiment of the computer data communication control system according to the present invention will be described in detail with reference to FIG.

In FIG. 1, the data transmitting and receiving circuits include an SP conversion circuit 1 that converts serial data to parallel data, a PS conversion circuit 2 that converts parallel data to serial data. Reception data transmission/reception circuit 3 for receiving data of a certain length
, transmission data F for transmitting data of a fixed length
IFO circuit 4, address match detection circuit 7 for detecting match between the address data of the received signal and the address of the device itself
, a reception control circuit 5 activated by the address coincidence detection circuit, and a transmission control circuit 6 for assembling transmission data also activated by the address coincidence detection circuit. , a reception data ready signal line RxS that notifies the processor of the arrival of reception data, a transmission data ready signal line TxS that notifies the processor of the completion of transfer of reception data, and a processor data bus interface circuit 8.

[Operation of the invention] The operation of the invention will be explained below with reference to FIG. As in the prior art, in FIG.
The FLL processor is a slave device○F...
For OFn, as shown in Fig. 3, a start flag FGs and a stop flag FGP indicate the beginning and end of data.
, slave device ○F□...OFn's address data AD and a serial data signal consisting of a data block DT of a constant length are transmitted at regular intervals. Slave device O
The processors F1...OFn receive this serial data using the data transmitting/receiving circuit shown in FIG. 1 connected to the transmitting data line TxD and receiving data line RxD shown in FIG. Here, received data 4 in Figure 1! The serial data signal input to RxD is S
It is converted into parallel data by the P conversion circuit, and then checked by the address match detection circuit 7 to see if the address data of the input signal matches the address data of the own device. Only when they match, the address match detection circuit 7 performs reception control. The circuit 5 is activated, and the data of the input signal is transferred to the received data transmitting/receiving circuit 5. At the same time, the reception control circuit 5 notifies the processors of the slave devices 10 Fl...OFn of the data reception using the reception data ready signal 1Rxs. Furthermore, in advance,
The data transferred to the transmission data transmission/reception circuit 4 by the processors of the slave devices OF□...OFn is assembled into the data configuration shown in FIG. 3 by the transmission control circuit 6 activated by the address data detection circuit 7 of the input signal. The parallel data obtained is converted into a serial data signal for each byte of data by the PSe conversion circuit 2 shown in FIG. 1, and sent to the reception data line shown in FIG. 2. At this time, the transmission control circuit 6 of FIG. 1 simultaneously uses the transmission data ready signal line TxS to communicate with the slave device ○F...
Notifies the OFn processor of the end of data transmission. The processor of the master device OF in FIG. 2 uses the same data transmitting and receiving circuit as in FIG.
...Receive the OFn transmission data. The processors of the slave devices ○F1...OFn in FIG. 2 connect the received data ready signal line RxS in FIG. After checking, if the data has arrived, the received data is transferred to the memory of the own device through program processing. Also, if there is transmission data, check the transmission data ready signal line TxS in Figure 1, and if the transmission of the previous data has been completed, program processing will transfer the memory data of the own device to the transmission data in Figure 1. Transfer to the transmitting/receiving circuit 4.

Furthermore, although the above embodiment describes the case where the communication format between the computer and the data device is 5DLC serial data communication, other synchronous serial data borrowing methods and asynchronous serial data borrowing methods can also be implemented. .

[Effects of the Invention] The computer data communication control system according to the present invention includes an address matching detection means for detecting whether the address of received data is addressed to the local station and outputting a reception flag, and activating the reception flag to It is configured to include a received data storage means for sequentially storing received data and a transmission data storage means for sequentially storing transmitted data, and to transmit and receive computer data according to a predetermined protocol via the reception and transmission data storage means according to the reception flag. Therefore, the feature is that the master device does not start the interrupt program of the slave device. For this reason, each slave device is equipped with a data transmitting/receiving circuit that can detect the arrival of serial data from the master device, automatically receive data of a certain length, and at the same time convert the data of a certain length into serial data and transmit it. This makes it possible for the slave device to communicate efficiently in a multiprocessor system without restricting the processor, and has the effect that a multiprocessor system with strict time and timing can be configured relatively easily. Moreover, the overhead of program processing associated with interrupt and interruption time is reduced, and the reliability of the program is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer data communication control system according to the present invention, FIG. 2 is a system diagram of a computer data communication control system, FIG. 3 is a data configuration diagram of FIG. 2, and FIG.
This figure is a block diagram of a conventional computer data communication control system, and FIG. 5 is a flowchart of an interrupt processing program related to FIG. 2. 3... Received data transmitting/receiving circuit (receiving data storage means) 4...... Transmitting data transmitting/receiving circuit (transmitting data storing means) 5... Receive control circuit (protocol tool) ) 6...Transmission control circuit (protocol tool) 7...Address match detection circuit (address match detection means) Agent Patent attorney Moritani Figure 1 Figure 2? F. Figure 3 SB Figure 4

Claims (1)

[Claims] address matching detection means for detecting whether the address of received data is addressed to the local station and outputting a reception flag; reception data storage means for sequentially storing the reception data by activating the reception flag; and reception data storage means for sequentially storing the reception data by activating the reception flag; 1. A computer data communication control system, characterized in that computer data is transmitted and received according to a predetermined protocol via a transmission data storage means for storing data and a transmission data storage means according to the reception flag.