JPH0683227B2 - Computer data communication control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a computer data communication control system,
In particular, it relates to a computer data communication control system using a multiprocessor.

[Prior Art] SDLC has been conventionally used as a computer / data communication control method.
Second method (Synchronous Data Line Control)
There are those shown in FIGS. 3, 3 and 4. In FIG. 2, the master device O is used as a computer data device.
Master device O in F ₀ , slave devices OF ₁ , OF ₂ ... OFn
The F ₀ processor (not shown) is connected to the transmission data line TxD and the reception data line RxD via the data transmission / reception circuit of FIG.

Processors (not shown) of the slave devices OF ₁ ... OFn are connected to the second transmission data line TxD and the reception data line RxD via the data transmission / reception circuit of FIG. In the slave devices OF ₁ ... OFn, the reception data line RxD shown in FIG. 4 is the transmission data line TxD, and the transmission data line TxD is the reception data line RxD.
Read as.

As shown in Fig. 3, the structure of communication data is the least significant bit LS.
B to start flag FGs, address data AD, data block DT and stop flag FGp.

The data transmission / reception circuit includes a serial / parallel conversion circuit 1 for converting serial data into parallel data, a parallel / serial conversion circuit 2 for converting parallel data into serial data, and a reception data buffer circuit 1a for temporarily storing reception data. , A transmission data buffer circuit 2a for temporarily storing transmission data, a data reception detection circuit 7 for detecting the arrival of data, a reception control circuit 5 activated by the data reception detection circuit at the time of data arrival, data Is formed of an interrupt signal line IS for notifying the processor of the arrival of the data, a transmission control circuit 6, a transmission data ready signal line TxS indicating the end of data transmission, and a data bus interface circuit 8 of the processor.

In the computer data communication control system of this configuration, the processor of the master device OF _{0 in} FIG.
As shown in FIG. 3, it is composed of a start flag FGs, a stop flag FGp, address data AD to the slave device OF ₁ ... OFn, and a data block DT of a fixed length for F ₁ ... OFn. To transmit the serial data signal.

The processors of the slave devices OF ₁ ... OFn of FIG. 2 receive data by the interrupt signal line IS output from the reception detection circuit 7 of the data transmission / reception circuit of FIG. 4 connected to the transmission data line TxD and the reception data line RxD. Then, the ongoing processing is immediately interrupted and the interrupt processing program 10 shown in FIG. 5 is executed. First, the address data is received from the reception data buffer circuit 1a shown in FIG. 4, and if the address does not match the preset address of the own device, the judgment in the judgment box 12 is made to terminate the interrupt processing via the return 18. . The interrupted program resumes the interrupted process. If the addresses match in the judgment in the judgment box 12, the number of blocks of the data to be read next is set in the memory for counting in the processing 13. When the number of bytes set by the processing 14, 15, 16 and the judgment box 17 has been transferred to the memory area of the own device, the interrupt processing is terminated via the return 18. Further, the transmission is carried out by the program processing at appropriate timing so that the transmission does not collide with other slave devices OF ₁ ... OFn.

[Problems to be Solved by the Invention] Since the conventional computer data communication control system is configured as described above, in order to transmit a fixed length of serial data from the master device OF ₀ side at a time, the slave device needs a fixed time. it is necessary to restrain the processor apparatus oF ₁ ... OFn side, there is a drawback that strict other processing times and the timing processor of the slave device oF ₁ ... OFn side is difficult to program processed simultaneously.

[Object of the Invention] The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and a computer capable of transmitting / receiving a fixed length of serial data between multiprocessors without going through a processor on the slave device side. An object is to provide a data communication control method.

[Means for Solving the Problem] In order to achieve this object, a computer data communication control system according to the present invention provides a reception data line and a transmission data line between a master device and a slave device, and a reception data line is used. Serial / parallel conversion circuit that converts the input fixed length serial data to parallel data, the parallel / serial conversion circuit that converts the fixed length parallel data to serial data and output from the transmission data line, and the received data address An address match detection circuit that detects whether the data matches the address data of the device itself, a reception control circuit and a transmission control circuit that are activated simultaneously by the address match detection circuit when both address data match, and a serial / parallel conversion circuit is used for conversion. The received parallel data is sent to the receiving control circuit. Entered,
The receive data FIFO circuit and the transmit data that are output according to the input order are input, and the transmit data FIFO circuit that is output to the parallel / serial conversion circuit by the transmit control circuit according to the input order, and the receive data
Provided is a data bus interface circuit for transmitting the reception data output from the FIFO circuit to the memory of the slave device having the address data via the data bus and transmitting the transmission data from the memory of the slave device to the transmission data FIFO circuit. It is a thing.

[Embodiment of the Invention] An embodiment of a computer data communication control system according to the present invention will be described below in detail with reference to FIG.

In FIG. 1, a data transmission / reception circuit includes a serial / parallel conversion circuit 1 for converting serial data into parallel data, a parallel / serial conversion circuit 2 for converting parallel data into serial data, and a reception for receiving a fixed length of data. The data FIFO circuit 3, the transmission data FIFO circuit 4 for transmitting a fixed length of data, the address match detection circuit 7 for detecting the match between the address data of the received signal and the address of the own device, and the address match detection circuit Reception control circuit 5, a transmission control circuit 6 for assembling transmission data also activated by the address coincidence detection circuit, and a processor (not shown)
Received data ready signal line that informs the incoming of incoming data to the
RxS, a transmission data ready signal line TxS for notifying the end of transfer of received data, and a processor data bus interface circuit 8.

[Operation of the Invention] The operation of the computer data communication control system according to the present invention will be described below with reference to FIG.

As in the case of the prior art, in FIG. 1 the processor (not shown) of the master device OF ₀ is the slave device OF ₁
For OFn, as shown in FIG. 3, a start flag FGs indicating the beginning and end of data, a stop flag FGp, a slave device OF ₁ ... A serial data signal including address data AD of OFn and a data block DT of a fixed length are transmitted. It is sent at regular intervals. Processors (not shown) of the slave devices OF ₁ ... OFn receive this serial data using the first data transmission / reception circuit connected to the transmission data line TxD and the reception data line RxD of FIG. Here, the serial data signal input to the reception data RxD of FIG. 1 is converted into parallel data by the serial / parallel conversion circuit 1 for each 1-byte data, and the address data of the input signal is further converted by the address coincidence detection circuit 7 into It is checked whether the address data of its own device match, and only when they match, the address matching detection circuit 7 activates the reception control circuit 5, and the data of the input signal is transferred to the reception data FIFO circuit 3. At this time, at the same time, the reception control circuit 5 uses the reception data ready signal line RxS to make the slave device OF ₁ ...
Notify OFn processor that data has been received. Further, the data transferred to the transmission data FIFO circuit 4 by the processor of the predetermined slave device OF ₁ ... OFn is transmitted by the transmission control circuit 6 activated by the address data detection circuit 7 of the input signal to the data structure shown in FIG. The parallel data thus assembled is converted into a serial data signal for each byte data by the parallel / serial conversion circuit 2 in FIG. 1 and sent out to the reception data line in FIG. At this time, the transmission control circuit 6 shown in FIG.
Uses the transmission data ready signal line TxS to notify the processors of the slave devices OF ₁ ... OFn that the data transmission is completed. Processor second master device OF _0, using the same data transmission and reception circuit and the first figure, the slave device OF ₁ ... O
Receive the transmission data of Fn. Slave device OF _{1 in} Fig. 2
... The processor of OFn confirms the reception data ready signal line RxS in FIG. 1 at the processing time that is convenient for itself within the period of data transmission of the master device OF _{0 to} the own device, and if data is received, The received data is transferred to the memory (not shown) of the device itself by the program processing. Also,
If there is transmission data, check the transmission data ready signal line TxS in FIG. 1, and if the transmission of the previous data is completed,
The memory data of the own device is transferred to the transmission data FIFO circuit 4 of FIG. 1 by the program processing.

Further, in the above-described embodiment, the case where the communication format between the computer and the data device is the serial data communication of the SDLC method has been described, but the same can be applied to other synchronous serial data communication methods and asynchronous serial data communication methods. .

[Effects of the Invention] As is apparent from the above description, in the computer data communication control method according to the present invention, the master device does not activate the interrupt program of the slave device, and the transmission data FIFO circuit and the reception data of the slave device are received. Since the master device sends and receives the send data and receive data directly from the FIFO circuit, the slave device's processor is not restricted and efficient multi-processor system communication is possible. In addition, the overhead of program processing due to interruption and interruption time is reduced, and the reliability of the program is improved.

[Brief description of drawings]

1 is a block diagram of a computer data communication control system according to the present invention, FIG. 2 is a system diagram of a computer data communication control system, FIG. 3 is a data configuration diagram of FIG. 2, and FIG.
FIG. 5 is a block diagram of a conventional computer data communication control system, and FIG. 5 is a flow chart of an interrupt processing program according to FIG. OF ₀ …… Master device OF ₁ …… OFn …… Slave device 1 …… Serial / parallel conversion circuit 2 …… Parallel / serial conversion circuit 3 …… Received data FIFO circuit 4 …… Transmission data FIFO circuit 8 …… Data bus interface Circuit RxD …… Received data line TxD …… Sent data line BUS …… Data bus

Claims (1)

[Claims] 1. A master device (OF ₀ ), a slave device (OF ₁ ,
A serial / parallel conversion circuit (RxD) and transmission data line (TxD) are provided between OF ₂ ... OFn to convert serial data of a fixed length input through the received data line into parallel data. 1), a parallel / serial conversion circuit (2) for converting parallel data of a fixed length into serial data and outputting the serial data from the transmission data line, and an address match for detecting a match between the address data of the received data and the address data of the own device. A detection circuit (7), a reception control circuit (5) and a transmission control circuit (6) that are simultaneously activated by the address coincidence detection circuit when both address data match, and a parallel converted by the serial / parallel conversion circuit. Received data that is input by the reception control circuit and is output according to the input order. The FIFO circuit (3) and the transmission data are input, and the transmission control circuit outputs the transmission data FIFO circuit (4) to the parallel / serial conversion circuit according to the input order, and the reception data FIFO circuit outputs the transmission data. Received data is transferred to the data bus (BU
A data bus interface circuit (8) for sending the address data to the memory of the slave device via S) and sending the send data from the memory of the slave device to the send data FIFO circuit. Computer data communication control method.