JPS55112638A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS55112638A
JPS55112638A JP2010779A JP2010779A JPS55112638A JP S55112638 A JPS55112638 A JP S55112638A JP 2010779 A JP2010779 A JP 2010779A JP 2010779 A JP2010779 A JP 2010779A JP S55112638 A JPS55112638 A JP S55112638A
Authority
JP
Japan
Prior art keywords
cpu1
flag
detection circuit
control circuit
dma control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010779A
Other languages
Japanese (ja)
Inventor
Yukihiko Ikoma
Mineji Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP2010779A priority Critical patent/JPS55112638A/en
Publication of JPS55112638A publication Critical patent/JPS55112638A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To enable data transfer, to reduce the burden in CPU and to increase the utility, by performing interruption to the control circuit only when the detection circuit detects the start flag or end flag.
CONSTITUTION: The flag detection circuit 7 interrupts CPU1 by detecting the start flag F1 of the data frame H, and CPU1 starts the timer 8 and outputs HLDA signal to the direct memory access DMA control circuit5. The DMA control circuit 5 controls the memory 6 and stores the data frame H to a given area. Further, when the flag detection circuit 7 detects the end flag F2 of the data frame H, interruption is made to CPU1, and CPU1 resets the DMA control circuit 5. Accordingly, CPU1 can only control the DMA control circuit 5 only when interruption is made from the flag detection circuit 7.
COPYRIGHT: (C)1980,JPO&Japio
JP2010779A 1979-02-22 1979-02-22 Data transfer system Pending JPS55112638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010779A JPS55112638A (en) 1979-02-22 1979-02-22 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010779A JPS55112638A (en) 1979-02-22 1979-02-22 Data transfer system

Publications (1)

Publication Number Publication Date
JPS55112638A true JPS55112638A (en) 1980-08-30

Family

ID=12017884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010779A Pending JPS55112638A (en) 1979-02-22 1979-02-22 Data transfer system

Country Status (1)

Country Link
JP (1) JPS55112638A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364150A (en) * 1986-09-04 1988-03-22 Matsushita Commun Ind Co Ltd Transferring method for frame form data
JPH01246941A (en) * 1988-03-29 1989-10-02 Aiphone Co Ltd System for controlling communication of computer data
JPH02224542A (en) * 1989-02-27 1990-09-06 Nec Corp Communication controller
JPH0311848A (en) * 1989-06-09 1991-01-21 Nec Corp Communication controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853643A (en) * 1971-11-08 1973-07-27
JPS5391543A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for hdlc circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4853643A (en) * 1971-11-08 1973-07-27
JPS5391543A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for hdlc circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6364150A (en) * 1986-09-04 1988-03-22 Matsushita Commun Ind Co Ltd Transferring method for frame form data
JPH01246941A (en) * 1988-03-29 1989-10-02 Aiphone Co Ltd System for controlling communication of computer data
JPH0683227B2 (en) * 1988-03-29 1994-10-19 アイホン株式会社 Computer data communication control method
JPH02224542A (en) * 1989-02-27 1990-09-06 Nec Corp Communication controller
JPH0311848A (en) * 1989-06-09 1991-01-21 Nec Corp Communication controller

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