JPS55103618A - Multi-processor system - Google Patents

Multi-processor system

Info

Publication number
JPS55103618A
JPS55103618A JP1089879A JP1089879A JPS55103618A JP S55103618 A JPS55103618 A JP S55103618A JP 1089879 A JP1089879 A JP 1089879A JP 1089879 A JP1089879 A JP 1089879A JP S55103618 A JPS55103618 A JP S55103618A
Authority
JP
Japan
Prior art keywords
processor
time
slave
slave processor
sends
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1089879A
Other languages
Japanese (ja)
Inventor
Tsutomu Yanagisawa
Harumitsu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1089879A priority Critical patent/JPS55103618A/en
Publication of JPS55103618A publication Critical patent/JPS55103618A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent runaway of a processor by causing a master processor to detect rapidly anomaly of a slave processor.
CONSTITUTION: Master processor 1 sets a start instruction and character information to a print buffer and sends an interrupt signal to slave processor 2 to start the count operation of a time supervisory timer. In case that end information from slave processor 2 is not received after a set time from start of the time supervisory timer, master processor 1 sends a reset signal to slave prcessor 2. When the reset signal is inputted, slave processor 2 becomes the initial state. Master processor 1 decides time-out as the first or the second; and in case of the first time-out, master processor sets the start instruction and character information to the print buffer again and sends the interrupt signal to slave processor 2. When time-out occurs again, slave processor 1 resets slave processor 2.
COPYRIGHT: (C)1980,JPO&Japio
JP1089879A 1979-02-01 1979-02-01 Multi-processor system Pending JPS55103618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1089879A JPS55103618A (en) 1979-02-01 1979-02-01 Multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1089879A JPS55103618A (en) 1979-02-01 1979-02-01 Multi-processor system

Publications (1)

Publication Number Publication Date
JPS55103618A true JPS55103618A (en) 1980-08-08

Family

ID=11763110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1089879A Pending JPS55103618A (en) 1979-02-01 1979-02-01 Multi-processor system

Country Status (1)

Country Link
JP (1) JPS55103618A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156798A (en) * 1985-12-27 1987-07-11 オムロン株式会社 Electronic settlement processing terminal
JPH01233525A (en) * 1988-03-14 1989-09-19 Fujitsu Ltd Computer
JPH0228735A (en) * 1988-07-19 1990-01-30 Fujitsu Kiden Ltd Computer supervisory device
JPH0554045A (en) * 1991-08-28 1993-03-05 Nec Corp Pos terminal equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122342A (en) * 1974-08-19 1976-02-23 Tokyo Shibaura Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122342A (en) * 1974-08-19 1976-02-23 Tokyo Shibaura Electric Co

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156798A (en) * 1985-12-27 1987-07-11 オムロン株式会社 Electronic settlement processing terminal
JPH01233525A (en) * 1988-03-14 1989-09-19 Fujitsu Ltd Computer
JPH0228735A (en) * 1988-07-19 1990-01-30 Fujitsu Kiden Ltd Computer supervisory device
JPH0554045A (en) * 1991-08-28 1993-03-05 Nec Corp Pos terminal equipment

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