JPS5537643A - Multiprocessor system trouble processing system - Google Patents

Multiprocessor system trouble processing system

Info

Publication number
JPS5537643A
JPS5537643A JP11031478A JP11031478A JPS5537643A JP S5537643 A JPS5537643 A JP S5537643A JP 11031478 A JP11031478 A JP 11031478A JP 11031478 A JP11031478 A JP 11031478A JP S5537643 A JPS5537643 A JP S5537643A
Authority
JP
Japan
Prior art keywords
trouble
fcu4
signal
ofl
cpd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11031478A
Other languages
Japanese (ja)
Other versions
JPS592943B2 (en
Inventor
Toshio Awaji
Kazumi Endo
Yoshinori Hori
Takeshi Kawasaki
Takahiko Yamada
Masato Suyama
Shiro Manabe
Tadashi Koizumi
Yoshiaki Tokita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP53110314A priority Critical patent/JPS592943B2/en
Publication of JPS5537643A publication Critical patent/JPS5537643A/en
Publication of JPS592943B2 publication Critical patent/JPS592943B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To improvo availability of a system by providing a trouble controller which receives a trouble signal from each processor an then instructs another processor to process the trouble.
CONSTITUTION: A multiprocessor system composed of coupled processors 1CP1-1W nCP1-n is equipped with trouble controller FCU4 which receives trouble signal CPD from each CP and then instructs another CP to process the trouble. Then, FCU4 selects one of CPs sending no signal CPD and transmits interruption signal FTL for trouble process indication. Each CP sends signal OFL information FCU4 of an off-line mode, and FCU4 selects one of CPs receiving neither signal CPD nor OFL on receiving OFL and sends signal FTL to indicate the trouble process. Then, FCU4, composed of wired logic, is simplified in constitution as much as prossible to suppress its own trouble occurrence to a minimum for release at the time of a trouble, thereby improving availability of the system.
COPYRIGHT: (C)1980,JPO&Japio
JP53110314A 1978-09-08 1978-09-08 Multiprocessor system failure handling method Expired JPS592943B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53110314A JPS592943B2 (en) 1978-09-08 1978-09-08 Multiprocessor system failure handling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53110314A JPS592943B2 (en) 1978-09-08 1978-09-08 Multiprocessor system failure handling method

Publications (2)

Publication Number Publication Date
JPS5537643A true JPS5537643A (en) 1980-03-15
JPS592943B2 JPS592943B2 (en) 1984-01-21

Family

ID=14532563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53110314A Expired JPS592943B2 (en) 1978-09-08 1978-09-08 Multiprocessor system failure handling method

Country Status (1)

Country Link
JP (1) JPS592943B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748858A (en) * 1980-09-09 1982-03-20 Nec Corp Manual exchanging system
JPS57101954A (en) * 1980-12-18 1982-06-24 Nec Corp Error information system of logical device
JPS57116492A (en) * 1981-01-10 1982-07-20 Nec Corp Decentralized control type switching system
JPS57209558A (en) * 1981-06-19 1982-12-22 Hitachi Ltd Emergency information system between processors
JPS62202239A (en) * 1986-03-03 1987-09-05 Hitachi Ltd Hot stand-by processing method for online program
WO2017163302A1 (en) * 2016-03-22 2017-09-28 株式会社東芝 Control apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748858A (en) * 1980-09-09 1982-03-20 Nec Corp Manual exchanging system
JPS57101954A (en) * 1980-12-18 1982-06-24 Nec Corp Error information system of logical device
JPS57116492A (en) * 1981-01-10 1982-07-20 Nec Corp Decentralized control type switching system
JPS6322675B2 (en) * 1981-01-10 1988-05-12 Nippon Electric Co
JPS57209558A (en) * 1981-06-19 1982-12-22 Hitachi Ltd Emergency information system between processors
JPS62202239A (en) * 1986-03-03 1987-09-05 Hitachi Ltd Hot stand-by processing method for online program
WO2017163302A1 (en) * 2016-03-22 2017-09-28 株式会社東芝 Control apparatus

Also Published As

Publication number Publication date
JPS592943B2 (en) 1984-01-21

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