JPS5567822A - Channel connection system - Google Patents

Channel connection system

Info

Publication number
JPS5567822A
JPS5567822A JP14100678A JP14100678A JPS5567822A JP S5567822 A JPS5567822 A JP S5567822A JP 14100678 A JP14100678 A JP 14100678A JP 14100678 A JP14100678 A JP 14100678A JP S5567822 A JPS5567822 A JP S5567822A
Authority
JP
Japan
Prior art keywords
data
processor
remote system
processors
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14100678A
Other languages
Japanese (ja)
Inventor
Mamoru Araya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14100678A priority Critical patent/JPS5567822A/en
Publication of JPS5567822A publication Critical patent/JPS5567822A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To enhance the data transmission efficiency by securing the free data transfer for the processor of the remote system between the processors and securing the monitor whether or not the data is under transfer to the processor of the self- system via the remote system at the data transfer request time to carry out the set-up control for synchronization.
CONSTITUTION: Channel connection unit 4 is provided between processors 1 and 2 which are to be connected, and the transmission data to be sent from one unit to the other is stored in unit 4. Then the free data transmission is secured for the processor of the remote system between processors 1 and 2, and the monitor is given to the processor of the self-system whether the data is under transmission or not by the remote system when the data transfer request is given. Thus the set-up control is carried out for synchronization. As a result, the data transfer efficiency can be increased.
COPYRIGHT: (C)1980,JPO&Japio
JP14100678A 1978-11-17 1978-11-17 Channel connection system Pending JPS5567822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14100678A JPS5567822A (en) 1978-11-17 1978-11-17 Channel connection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14100678A JPS5567822A (en) 1978-11-17 1978-11-17 Channel connection system

Publications (1)

Publication Number Publication Date
JPS5567822A true JPS5567822A (en) 1980-05-22

Family

ID=15281983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14100678A Pending JPS5567822A (en) 1978-11-17 1978-11-17 Channel connection system

Country Status (1)

Country Link
JP (1) JPS5567822A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578829A (en) * 1980-06-20 1982-01-18 Hitachi Ltd Input and output controller
JPS5983235A (en) * 1982-11-05 1984-05-14 Nec Corp Interface system between processors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS578829A (en) * 1980-06-20 1982-01-18 Hitachi Ltd Input and output controller
JPS5983235A (en) * 1982-11-05 1984-05-14 Nec Corp Interface system between processors

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