JPH06204964A - Ndf generating circuit for pointer processing circuit of digital transmission system - Google Patents

Abstract

PURPOSE:To provide an NDF generating circuit which can evade the increase of the circuit scale and the complication of the circuit structure. CONSTITUTION:A J1-J1 calculation part 7 calculates the bytes of the SPR data between the J1 bytes of two continuous frames to monitor whether the normal communication is carried out or not. Then a pointer value comparing part 10 compares the pointer value of the present frame with the pointer value of the precedent frame held by a precedent frame pointer value latching part 9 even though the monitoring result of the part 7 shows the abnormal communication. If the coincidence is confirmed between both pointer values, a normal state is decided and Normal NDF is produced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission system, for example, new synchronous multiplex communication such as SONET (Synchronous Optical NETwork), from a clock on the receiving side to a transmitting side on a relay device, a multiple conversion device, etc. The present invention relates to pointer processing when transferring to a clock, and particularly to a New Data Flag (NDF) generation circuit associated with the pointer processing.

[0002]

2. Description of the Related Art FIG. 1 shows SO as a digital transmission system.
FIG. 3 is a schematic diagram showing the structure of the STS frame format of NET. Here, for convenience of explanation, the multiplexing number is 1, that is, ST.
It is a schematic diagram which shows the frame format of S-1.

One frame of SONET is composed of 90 bytes × 9 lines, and is mainly composed of an overhead part which is a header for data for transmitting a frame synchronization signal or various auxiliary signals and a payload part for transmitting an information signal. I know. Each line consisting of 90 bytes is called a subframe, and the signal flow is from the beginning of the first line to the end.
It is repeated from the beginning of the second line to the end.

A frame synchronization signal,
It includes all the various signals necessary for transmission of multiple signals such as error monitoring code, channel identification signal, maintenance channel, and alarm signal. Taking the first line of the frame (first subframe) as an example, the first 3 bytes are fixed as overhead bytes (A1, A2, C1), and the subsequent 87 bytes are the payload part for data. Is. One byte of path overhead (hereinafter referred to as POH) bytes is located in the payload section at a position common to each subframe, and one frame constitutes the path overhead section.

The overhead part consisting of 3 bytes on the head side of each subframe is called a section overhead part for the first to third subframes, and a line overhead part for the other subframes.

As shown in the schematic diagram of FIG. 2, the overhead bytes H1 and H2 of the fourth line (fourth sub-frame), in other words, the overhead bytes H1 and H2 of the first line of the line overhead part, are used to store data. This is a pointer that specifies the J1 byte of the path overhead part, which is the start position. The H1 and H2 bytes of this overhead byte are both 16 bytes, and the lower 10 bits of them indicate the position of the J1 byte that is the first byte of the data in the same frame as a pointer value.

Specifically, the overhead bytes H1 and H2
The byte immediately after the H3 byte following the byte is the count value
Corresponding to the byte "0", the count value from the byte with the count value "0" to the J1 byte is stored in the overhead bytes H1 and H2 as pointer values.

The byte immediately after this H3 byte is "
0 ", and the count value that is continuous in each byte of the payload section over each subframe is SPE (Synchrounous Paylo
ad Envelope) address.

FIG. 3 shows a schematic diagram of a frame format to which an SPE address is added. Here, for example, if the J1 byte is located in the byte next to the H3 byte, the pointer values stored in the H1 and H2 bytes of the overhead byte are H1 = XXXXXX00, H2 = 00000000, that is, SPE address = "0". If it is located at the byte next to the K3 byte, H1 = XXXXXX00, H2 = 01010111, that is, S
If PE address = "87" and the byte is located before the H1 byte, H1 = XXXXXX11, H2 = 000011
10, that is, SPE address = "782". However, the bit in the X part has no meaning as a pointer value.

By the way, as shown in the schematic diagram of FIG. 2, the upper 4 bits of the H1 byte are NDF (New Data F).
lag), which is used as information indicating whether or not the pointer value has been changed.

Specifically, when normal data communication is normally performed, the NDF has a value of "0110".
Normal NDF is sent. However, for example, when the device power is turned on, when a line error occurs (alarm occurrence, input clock cutoff, etc.), when recovery is performed after a memory slip occurs, or when pointer control is performed when staff control is performed. When there is a change in the sending pointer value excluding the change, NDF ENABLE having a value of "1001" is sent as the NDF.

On the other hand, on the receiving side, when Normal NDF is received, the receiving process may be continued as before, but when NDF ENABLE is received, the pointer value used in the subsequent receiving process. Should be immediately changed to the pointer value contained in the H1 and H2 bytes sent with NDF ENABLE. This is to cope with a recovery after a line failure or the like or a sudden change in the pointer value.

Under these circumstances, conventionally, the monitoring for each condition when NDF ENABLE is sent, the monitoring of the change of the pointer value, and the No. based on the staff control are performed.
It manages the sending of rmalNDF and NDF ENABLE. However, in such a conventional method, it is necessary to monitor all NDF sending conditions every time pointer processing is performed, which causes an increase in circuit scale and complexity.

FIG. 4 is a block diagram showing a configuration example of a pointer processing circuit and an NDF generating circuit of a conventional digital transmission system. In FIG. 4, reference numeral 1 indicates a pointer value receiving unit, which receives the pointer value from the H1 and H2 bytes of each frame in the received data received from the outside. The pointer value received by the pointer value receiving unit 1 is given to the J1 pulse generating unit 2.

The J1 pulse generation unit 2 includes a pointer value reception unit 1
A pulse signal (hereinafter referred to as a J1 pulse) is generated at a timing corresponding to the position of the J1 byte according to the pointer value received from the memory unit 3 and given to the memory unit 3.

The memory unit 3 is supplied with the J1 pulse given from the J1 pulse generating unit 2, the received data inputted from the outside, the received clock, and the transmitted clock, and between the both clocks. The staff control unit 4 controls the staff for synchronizing the above. Memory part 3
Functions as a buffer memory, temporarily buffers the received data input in synchronization with the reception clock, and outputs the transmission data in synchronization with the transmission clock by outputting the data according to the stuff control by the stuff control unit 4.

At this time, each pointer value in the frame of the transmission data is calculated by the pointer value calculation unit 5, and this pointer value is calculated by the pointer insertion unit 6 in H1 of each frame.
It is inserted in the lower 10 bits of the H2 byte. Specifically, the pointer value calculation unit 5 determines the pointer value depending on which of the addresses up to the address "782" coincides with the timing of the J1 pulse with the byte next to the H3 byte of the SPE address as the address "0". decide.

On the other hand, the pointer insertion unit 6 has an NDF generation circuit.
NDF is given from 20 and inserted into the upper 4 bits of the H1 byte of each frame when the above pointer value is inserted.

Although the details of the configuration of the NDF generation circuit 20 are omitted, it is usually a Normal NDF having a value of "0110".
As described above, for example, when the power is turned on, when a line error occurs (alarm occurs, input clock is cut off, etc.), and when recovery is performed after a memory slip occurs, or when staff control is performed. If there is a change in the send pointer value except for the change in the pointer value of
An NDF ENABLE having a value of 1001 ”is generated, inserted into a frame of transmission data and transmitted.

Therefore, the NDF generation circuit 20 uses Norm as NDF.
al It consists of various circuits to monitor whether NDF should be transmitted or NDF ENABLE should be transmitted, and monitoring by all of these circuits is required every time pointer processing is performed. Therefore, the circuit scale is increased and the complexity is increased.

[0021]

As described above, the conventional
The NDF generation circuit has the problems of increased circuit scale and complexity.

The present invention has been made in view of the above circumstances, and is an NDF capable of avoiding an increase in circuit scale and complication.
The purpose is to provide a generation circuit.

[0023]

FIG. 5 shows a block diagram of a principle configuration example of a pointer processing circuit of a digital transmission system and an NDF generating circuit of the present invention. In addition, in FIG.
Reference numerals 1, 2, 3, 4, 5, 6 indicate the same parts as those in the conventional example described above.

In the present invention, it is designated by the reference numeral 20.
The NDF generation circuit is characterized by being configured as follows. The NDF generation circuit 20 of the present invention is mainly composed of J1−
It is composed of an inter-J1 calculation unit 7, an NDF ENABLE mask unit 8, a previous frame pointer value latch unit 9, a pointer value comparison unit 10, and the like.

A pulse signal (hereinafter referred to as J1 pulse) indicating the timing of the J1 byte of each frame is output from the memory unit 3 similar to the conventional one, and the pointer value calculation unit 5 and J1−.
It is given to the calculation unit 7 between J1s. The pointer value calculation unit 5 calculates the pointer value as in the conventional example, and supplies the value to the previous frame pointer value latch unit 9, the pointer value comparison unit 10 and the pointer insertion unit 6.

The previous frame pointer value latch unit 9 latches the pointer value given from the pointer value calculation unit 5 until the timing of the next frame, thereby latching it as the pointer value of the previous frame. The pointer value of the previous frame latched by the previous frame pointer value latch unit 9 is given to the pointer value comparison unit 10.

The pointer value comparison unit 10 is a pointer value calculation unit 5
The pointer value of the current frame given by the above is compared with the pointer value of the previous frame latched by the previous frame pointer value latch unit 9. The comparison result by the pointer value comparison unit 10 is given to the NDF ENABLE mask unit 8.

The J1-J1 calculator 7 calculates the interval between the J1 byte of the previous frame and the J1 byte of the current frame, that is, J1 of the previous frame.
S from the byte position to the J1 byte position of the current frame
The number of bytes of PE data is calculated, and the result is given to the NDF ENABLE mask unit 8. The calculation result by the J1-J1 calculation unit 7 is 783 bytes during normal operation, as is clear from the SONET frame format shown in Fig. 1. Therefore, if the actual calculation result is 783 bytes, the current frame The pointer value of is supposed to be the same as the pointer value of the previous frame, and Normal NDF is generated.

On the other hand, for example, when stuffing occurs as a result of stuffing control by the stuffing control unit 4, the pointer value also changes, but the number of SPE data is 783, which is the same number, so Normal NDF is generated. . However, when the power is turned on or the position of the J1 byte changes abruptly, the number of SPE data does not necessarily become 783, so the pointer value of the current frame does not become the same as the pointer value of the above frame, NDF ENABLE indicating that the pointer value has been changed is output from the J1-J1 calculator 7.

The NDF ENABLE masking unit 8 masks the NDF ENABLE output from the J1-J1 calculating unit 7 when the comparison results by the pointer value comparing unit 10 are the same. That is, during normal operation, the pointer value of the current frame is the same as the pointer value of the frame, so Normal NDF is output. However, if for some reason the interval between the J1 byte of the previous frame and the J1 byte of the current frame cannot be calculated by the J1-J1 calculator 7, or even if it can be calculated, it is a normal value 783. If they are different, the NDF ENABLE signal output from the J1-J1 calculation unit 7 is set to the NDF ENABLE mask unit 8 in order to give priority to the normal state detected by the matching of the pointer values in the pointer value comparison unit 10. Normal NDF is output to the outside by masking with.

The pointer insertion unit 6 is a pointer value calculation unit 5
The NDF (Normal NDF or NDF ENABLE) given from the NDF ENABLE mask part 8 and the pointer value given from the are inserted into H1 and H2 bytes of each frame of transmission data and transmitted.

[0032]

Therefore, in the NDF generation circuit of the present invention, basically, the J1-J1 calculation unit 7 calculates the number of bytes of the SPE data between the J1 bytes of two consecutive frames so that the normal communication is performed. The pointer value comparison unit 10 monitors the pointer value of the previous frame and the pointer value of the current frame even when the monitoring result in the J1 to J1 calculation unit 7 detects an abnormal state. And are compared, and if they match, it is considered normal and a Normal NDF is generated.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

FIG. 6 shows a circuit diagram of a specific configuration example of the pointer processing circuit of the digital transmission system and the NDF generating circuit of the present invention. Specifically, the pointer value calculation unit 5 is composed of an up counter 51 and a flip-flop 52.

In the up counter 51, the data input terminal is always "0", and the load input terminal is H3 indicating the position of H3 byte.
As for the pulse, the SPE clock indicating the SPE byte position is input to the clock pin. Therefore, when the H3 pulse is input, the up counter 51 starts the up counting of the SPE clock with "0" as the initial value. That is, the count value of the up counter 51 indicates the SPE byte.

On the other hand, in the flip-flop 52, the count value of the up counter 51 is input to the data input terminal, the J1 pulse is input to the enable input terminal, and the SPE clock is input to the clock terminal. Therefore, the flip-flop 52
Holds the count value of the up counter 51 in synchronization with the J1 pulse, and outputs it to the previous frame pointer value latch unit 9 and the pointer value comparison unit 10.

The previous frame pointer value latch unit 9 is specifically composed of a flip-flop 91. In the flip-flop 91, the output of the flip-flop 52 of the pointer value calculator 5 is input to the data input terminal, the send pointer value latch timing signal is input to the enable input terminal, and the SPE clock is input to the clock terminal. In addition,
The send pointer value latch timing signal is a signal that indicates the timing at which the NDF to be sent and the value of the pointer value are fixed. Therefore, the flip-flop 91 inputs and holds the value held by the flip-flop 52 of the pointer value calculation unit 5 in synchronization with the sent pointer value latch timing signal, and outputs it to the pointer insertion unit 6.

The pointer value comparison unit 10 is specifically composed of an EXOR gate 100. This EXOR gate 100 has
The output of the flip-flop 91 of the previous frame pointer value latch unit 9 and the output of the flip-flop 52 of the pointer value calculation unit 5 are input. Therefore, EXOR gate 100
Outputs a signal "L" when the output of the flip-flop 52 and the output of the flip-flop 91 match, and outputs a signal "H" when they do not match. This ex
The output of the OR gate 100 is given to the NDF ENABLE mask section 8.

The J1-J1 calculator 7 is specifically composed of an up-counter 71, a flip-flop 72 and a "783" mismatch detection circuit 73. In the up counter 71, "1" is always input to the data input terminal, J1 pulse is input to the load input terminal, and the SPE clock indicating the SPE byte position is input to the clock terminal.

Therefore, when the J1 pulse is input, the up counter 71 starts up counting the SPE clock with "1" as the initial value. That is, the count value of the up counter 71 indicates the number of SPE bytes from the J1 byte of a certain frame to the J1 byte of the next frame.

On the other hand, in the flip-flop 72, the count value of the up counter 71 is input to the data input terminal, the J1 pulse is input to the enable input terminal, and the SPE clock is input to the clock terminal. Therefore, the flip-flop 72
Holds the count value of the up counter 51 in synchronization with the J1 pulse and outputs it to the “783” mismatch detection circuit 73.

The "783" mismatch detection circuit 73 outputs a signal "when the output of the flip-flop 72 does not match" 783 ".
When "H" matches "783", the signal "L" is output respectively. The output of the "783" mismatch detection circuit 73 is output to the NDF ENABLE mask unit 8.

The NDF ENABLE mask section 8 is specifically composed of an AND gate 81 and a flip-flop 82. AND
The gate 81 includes the EXOR gate 10 of the pointer value comparison unit 10 described above.
0 output and "783" mismatch detection circuit of J1-J1 calculator 7
The output of 73 is input. Therefore, the AND gate 81 outputs the signal "H" only when both inputs are "H". That is, it is detected by the calculation unit 7 between J1 and J1 that the number of bytes between two consecutive J1 bytes is not "783", and that the pointer values of the two frames do not match, the pointer value comparison unit The AND gate 81 outputs the signal "H" only when detected by 10.

In other words, even when the number of bytes between two consecutive J1 bytes is not "783",
When the pointer values of both frames match, the output of the AND gate 81 becomes "L". This AND gate 81
The output of "H" means that NDF is NDF ENAB
It is instructed to send LE and it is "L".
It means that transmission of Normal NDF is instructed as NDF.

The data input terminal of the flip-flop 82 is
The output of the AND gate 81, the send pointer value latch timing signal to the enable input terminal, and the S
Each PE clock is input. Therefore, the flip-flop 82 holds the output of the AND gate 81 in synchronization with the sent pointer value latch timing signal and outputs it to the pointer insertion unit 6.

If the output signal of the flip-flop 82 is the output of the NDF ENABLE mask section 8 and its value is "H" when it is given to the pointer inserting section 6, the pointer inserting section 6 is NDF as NDF. Send ENABLE, and if it is "L", send Normal NDF as NDF.

The operation of the NDF generating circuit of the present invention will be described below together with the operation of the pointer processing circuit. Table 1 shows the output signal a of the J1 to J1 calculation unit 7, the output signal b of the pointer value calculation unit 5, and the previous frame pointer value for each of the four states in which NDF of Normal NDF or NDF ENABLE is generated. The output signal c of the latch unit 9, the output signal d of the pointer value comparison unit 10, and the output signal e of the AND gate 81 of the NDF ENABLE mask unit 8 are shown. In addition, Table 2
NDF ENABLE The NDF output from the mask unit 8 (whether it is Normal NDF or NDF ENABLE), the pointer value output, and the specific states of (1) to (4) are shown.

[0048]

[Table 1]

A signal is output from the memory unit 3 similar to the conventional one at the timing of the J1 byte of each frame and is given to the pointer value calculation unit 5 and the J1-J1 calculation unit 7. The pointer value calculation unit 5 calculates the pointer value as in the conventional example, and supplies the value to the previous frame pointer value latch unit 9, the pointer value comparison unit 10 and the pointer insertion unit 6.

The previous frame pointer value latch unit 9 latches the pointer value given from the pointer value calculation unit 5 until the timing of the next frame, thereby latching it as the pointer value of the previous frame. The pointer value of the previous frame latched by the previous frame pointer value latch unit 9 is given to the pointer value comparison unit 10.

The pointer value comparison unit 10 is a pointer value calculation unit 5
The pointer value of the current frame given by the above is compared with the pointer value of the previous frame latched by the previous frame pointer value latch unit 9.

Further, the calculation unit 7 between J1 and J1 uses the J1 of the previous frame.
Calculate the interval between the byte and the J1 byte of the current frame, that is, the number of bytes of SPE data from the J1 byte position of the previous frame to the J1 byte position of the current frame, and calculate the result as NDF ENA
It is given to the BLE mask unit 8. In the normal communication state, the calculation result by the J1 to J1 calculation unit 7 is 783 bytes, so if the actual calculation result is 783 bytes, the pointer value of the current frame is the pointer value of the previous frame. And the normal NDF is generated. This is
This is the state shown in (1).

On the other hand, when stuffing occurs as a result of stuffing control by the stuffing control unit 4, the pointer value also changes, but the number of SPE data is 783, which is the same number. Normal NDF is generated from. This is the state shown in (3) of Table 1.

However, when the power is turned on or the position of the J1 byte changes abruptly, the number of SPE data is not always 783, and the pointer value of the current frame is the same as the pointer value of the previous frame. However, NDF ENABLE is generated from the calculation unit 7 between J1 and J1. This is
This is the state shown in (4).

The NDF ENABLE mask unit 8 determines that the calculation result of the J1-J1 calculation unit 7 is not "783", but the pointer value comparison unit 10
When the comparison result by (1) is the same, that is, in the case of (2) in Table 1, the NDF ENABLE output from the calculation unit 7 between J1 and J1 is masked and the Normal NDF is output.

In the normal operation as shown in (1) of Table 1, the pointer value of the current frame is the same as the pointer value of the frame, so that the pointer value comparison unit 10 matches both pointer values. Is detected, and the calculation unit 7 between J1 and J1
Then, it is detected that the number of SPE data is "783". Therefore, the inputs to the AND gate 81 of the NDF ENABLE mask unit 8 both become "L", and the signal "L", that is, the signal indicating Normal NDF is output from the NDF ENABLE mask unit 8.

In the case of a long-term line error as shown in (4) of Table 1, when recovering from a memory slip, and when the power is turned on, the pointer value of the previous frame and the pointer of the current frame Since the values are different, the pointer value comparison unit 10 detects a mismatch between the pointer values, and J1-J1
The inter-computation unit 7 also detects that the number of SPE data is not "783". Therefore, the inputs to the AND gate 81 of the NDF ENABLE mask section 8 both become "H", so that the NDF ENABLE mask section 8 outputs a signal "H", that is, a signal indicating NDF ENABLE. In this case, the changed pointer value is also output.

When, for example, stuff control as shown in (3) of Table 1 occurs, the number of SPE data does not change but the pointer value changes within a range of ± 1. Therefore, the pointer value comparison unit 10 detects a mismatch between the pointer values, and the J1-J1 calculation unit 7 determines that the number of SPE data is "783".
Is detected. Therefore, the input to the AND gate 81 of the NDF ENABLE mask unit 8 is “1” from the calculation unit 7 between J1 and J1.
Since the pointer value comparison unit 10 changes to "H", the NDF ENABLE mask unit 8 outputs a signal "L", that is, Norm.
A signal indicating al NDF is output. In this case, Norm
al NDF is output, but the pointer value is updated.

However, in the case of stuff control, since the stuff signal is also transmitted when transmitting the pointer value of the previous frame, there is no problem if the pointer value of the current frame is ± 1 of the pointer value of the previous frame.

Even if the pointer value is transmitted with other pointer values, if the same pointer value is continuously received for three frames on the receiving side, the pointer value is updated even in the Normal NDF state, so that it remains as it is. There is no problem even if it is output.

However, in the case where an extremely short time line abnormality such as shown in (2) of Table 1 or a memory slip occurs, the pointer value is the same as the value transmitted in the previous frame. , The calculation result between J1 and J1 is “78”.
The NDF ENABLE signal may be output because it is not 3 ”. However, since the pointer value in this case is the same as the previous frame, NDF ENABLE should not be sent. It becomes necessary to mask with the NDF ENABLE mask section 8.

That is, the calculation result in the J1-J1 calculation unit 7 is "
Since it does not become 783 "," H "to NDF ENABLE mask part 8
However, since the pointer value comparison unit 10 detects that the pointer values of both frames match, NDF ENAB
Output “L” to the LE mask section 8. Therefore, NDF ENAB
Since the AND gate 81 of the LE mask section 8 outputs the signal "L", the NDF ENABLE mask section 8 outputs the signal "NDF ENABLE".
H "is not output, and a signal indicating Normal NDF"
L "is output.

As described above, since the meaningless NDF ENABLE transmission causes the receiving side to lose sight of the pointer, the provision of the NDF ENABLE mask section 8 is very useful.

If the J1 pulse which is the basis of NDF generation and pointer value calculation due to an internal fault is not input to the J1 to J1 calculation section 7 and the pointer value calculation section 5, J1 to J1
Since the calculation unit 7 cannot find the 783rd J1 pulse,
Output NDF ENABLE. Since the J1 pulse is not found in the pointer value calculation unit 5, the pointer value transmitted in the previous frame is retransmitted as it is. Since the pointer value transmitted in the previous frame is latched in the previous frame pointer value latch unit 9, if the J1 pulse is not found for a long time, the mask signal from the pointer value comparison unit 10 is used to calculate the J1 to J1 calculation unit. The NDF ENABLE signal output from 7 is masked by the NDF ENABLE mask section 8 and output, until the J1 pulse is found.
The same pointer value as the Normal NDF is output every frame. However, if the J1 pulse is found, it operates in the same manner as when recovering from, for example, a line failure.

[0065]

As described in detail above, according to the present invention,
From the relationship between the J1 byte position of the previous frame and the J1 byte position of the current frame, the number of SPE data between both J1 bytes can be calculated without the need to monitor multiple conditions for NDF generation and transmission in the conventional method. , By monitoring or controlling the pointer value to be sent, the NDF can be sent while satisfying the conditions for NDF generation and sending that were conventionally performed individually. Therefore, even if the conditions for NDF generation and transmission increase, the circuit scale does not expand.Since it is only necessary to monitor and control two states, the circuit scale can be reduced, the development man-hours can be reduced, and the power consumption can be reduced. Reduction is realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an STS frame format of SONET as a digital transmission system.

FIG. 2 is a schematic diagram showing a configuration of H1 and H2 bytes of a SONET STS frame format.

FIG. 3 is a schematic diagram of a SONET frame format to which an SPE address is added.

FIG. 4 is a block diagram showing a configuration example of a pointer processing circuit and an NDF generation circuit of a conventional digital transmission system.

FIG. 5 is a block diagram of a principle configuration example of a pointer processing circuit of a digital transmission system and an NDF generation circuit of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration example of a pointer processing circuit of a digital transmission system and an NDF generating circuit of the present invention.

[Explanation of symbols]

 7 J1-J1 calculation block 8 NDF ENABLE mask block 9 Previous frame pointer value latch block 10 Pointer value comparison block

Claims (1)

[Claims] 1. A byte (J1) at a byte position indicated by a pointer included in a specific byte (H1, H2) of a header portion of each frame, which constitutes one frame with a predetermined amount of data.
Of a digital transmission system that inputs a signal in which there is a specific data group arranged at a predetermined interval beginning with, and generates information (NDF) indicating whether the pointer has changed in the frame of the input signal In the NDF generation circuit in the pointer processing circuit, a previous frame pointer value latch unit (9) for holding the pointer of the previous frame of the input signal, a pointer of the current frame of the input signal, and the previous frame pointer value latch unit ( Pointer value comparison unit (10) that compares the pointer of the previous frame held in 9) with the byte at the byte position (J1) indicated by the pointer of the previous frame of the input signal and the pointer of the current frame. When the number of bytes of data between the byte (J1) at the byte position to be calculated is calculated and the calculation result does not match the predetermined value corresponding to one frame If the comparison result by the J1-J1 calculation unit (7) that outputs a signal (NDF ENABLE) indicating that the pointer value has changed and the pointer value comparison unit (10) match, the pointer value is A signal (N
(DF ENABLE) NDF ENABLE mask unit (8) for prohibiting the output from the J1-J1 calculation unit (7), the NDF generation circuit in the pointer processing of the digital transmission system.