JP3230550B2 - Phase control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit, and more particularly, to an NNI system (Networ system) input from a transmission device.
k Node Interface) STM frame (Syncronous
The present invention relates to a phase control circuit that controls the phase of data in a transfer mode and outputs the data to a receiving device.

[0002]

2. Description of the Related Art Conventionally, in a relay apparatus for relaying data transmitted in a data communication system, when the frequency of a data transmission clock differs from that of a reference apparatus clock in the relay apparatus, the relay apparatus comprises a dual port RAM or the like. The transmission data is clock-switched using the frame memory, and the transmission data is transmitted.

[0003] In particular, in data transfer using the NNI system, even when an error occurs in the data to be transmitted, the transmission data is transmitted to the opposing receiving apparatus in a format conforming to the NNI system. There is a need.
This is to prevent an abnormality of certain transmission data from being propagated to another frame.
The abnormality is notified using appropriate alarm transfer data.

FIG. 9 schematically shows a system configuration example using a conventional phase control circuit. Here, 81 and 82 are terminal devices (DTE), 81 is a transmitting device for outputting data, and 82 is a receiving device for receiving data. 83
Denotes an overhead (OH) identification unit 8
4, a phase control circuit 85, and an overhead (OH) insertion unit 86. Overhead identification unit 84
Is used to distinguish between overhead data including data used for transmission control or error control of data included in an STM frame according to the NNI system and payload data which is valid data, and is a reference for writing from a transmission clock to a frame memory. This is a part for performing an operation of generating a timing signal.

[0005] The phase control circuit 85 writes the payload data into the frame memory in accordance with the timing signal input from the overhead identification section 84 and absorbs the difference between the frequency of the transmission clock and the frequency of the receiving clock.
This section performs a stuff operation determined by the method and reads payload data from the frame memory at a phase synchronized with the receiving clock. Here, the transmission clock is a clock transmitted from the transmission device 81 in synchronization with the data, and the reception clock is a clock generated inside the device or transmitted from the reception device 82.

The overhead insertion unit 86 adds the overhead data to the payload data, assembles the data into a format conforming to the specification of the NNI system, and
2 is a part to be transmitted. The outline of the configuration of the data transmission system has been described above. The data transmission system uses a phase control circuit to absorb a phase shift between input and output and output data in a format defined by the NNI system.

FIG. 7 shows a format of one frame of the STM system. As shown in the figure, the minimum unit is a row composed of 9 bytes of overhead data (SOH) and 261 bytes of payload data, and (9 + 261) × 9 = 2430 bytes formed continuously for 9 rows constitute one frame. Form. That is, one frame is 9 bytes × 9
It is composed of an SOH part of a row and a payload part of 261 bytes × 9 rows.

In the fourth line of the STM frame, the first six bytes of the SOH portion contain an address indicating the head position of the payload data.
The remaining 3 bytes of the parts are the staff area for adjust the delivery phase of the data, the data is written as required.

For example, when the input transmission clock is faster than the reception clock, a part of the data actually transmitted is written to the stuff area in order to adjust the timing and the phase. Rarely absorbs clock differences. The 10th byte in the fourth line is the start position of the normal data, and this position is called a pointer point. FIG. 8 shows the structure of an STM frame developed on the time axis.
It is transmitted in 5 μs.

Next, FIG. 10 shows an example of a conventional phase control circuit. Here, the frame synchronization unit 91 is a part corresponding to the overhead identification unit 84 in FIG. 9, detects and analyzes input data in the STM frame format based on the transmission clock transmitted from the transmission device, and A payload information signal and an overhead information signal, which are timing signals for distinguishing the payload data from the overhead data, and a pointer pulse signal indicating a pointer point in the fourth row of the STM frame are generated.

FIG. 11 shows an example of a time chart of a conventional phase control circuit. Here, the payload information signal and the overhead information signal are the SOH of the STM frame.
A pointer pulse signal indicating a pointer point is a signal that rises at the beginning of the STM frame.

The frame memory 90 is a memory for writing and reading only the payload data of the input data. The payload counter 92 and the overhead counter 93 constitute a write control unit that writes the payload data to the frame memory 90.

The payload counter 92 inputs the above-mentioned payload information signal to an enable (EN) terminal,
While the payload data is being received, the enable state is enabled, the start of the counter is set by the pointer pulse signal, and the input transmission clock is counted to generate the write address of the frame memory 90.

The overhead counter 93 receives the overhead information signal as an enable input, sets the start of the counter by the pointer pulse signal, counts the transmission clock, and outputs a count value of the number of bytes corresponding to the overhead section. Things.

The comparator 94, the stuff counter 95, and the frame counter 96 constitute a read control unit for reading the payload data from the frame memory 90. Here, the comparator 94 is set by the pulse signal described above, and counts the count value from the counter 93 to a threshold value (Th).
And outputs the difference, that is, the stuff amount in one frame. As the threshold value (Th), 81, which is the number of bytes of the overhead portion when no stuff is generated, is set.

As shown in FIG. 11, when there is no stuffing, the count value from the counter 93 at the end of one frame is 81, and the numerical value output from the comparator 94 is 0. Further, as shown in FIG. 12, when the transmission clock is slower than the reception clock, for example, three bytes of invalid data are inserted into the payload part, and this part is also regarded as an overhead part. The count value from the counter 93 at the time is 84, and the numerical value output from the comparator 94 is +3.

When valid payload data is written in the 3-byte stuff area of the overhead section, the counter value from the counter 93 at the end of one frame is 78, and the numerical value output from the comparator 94 is −
It becomes 3.

The stuff counter 95 generates an inhibit signal for inhibiting reading in accordance with a numerical value output from the comparator 94. When there is no stuff and a numerical value 0 is input, as shown in FIG. 11, an inhibit signal for prohibiting reading for a period corresponding to 9 bytes of the overhead portion is transmitted. In the case of the numerical value +3, as shown in FIG. 12, reading is prohibited only for the period corresponding to 9 + 3 = 12 bytes, or in the case of the numerical value-3, for the period corresponding to 9-3 = 6 bytes. An inhibit signal is transmitted.

The frame counter 96 receives the inhibit signal from the stuff counter 95 as an enable input, counts a receiving clock inside the apparatus, and generates a read address of the frame memory 90.

The above is an example of the configuration of the conventional phase control circuit, which monitors the presence / absence of stuff for each NNI STM frame and determines the phase of the payload indicating the position of the payload data of the input frame. The phase of the output payload data is adjusted according to the fluctuation.

[0021]

However, when an abnormality occurs due to noise or instantaneous interruption on the transmission line, a situation is erroneously detected as "staff present" even though no staff has occurred. Although it is very rare, existing phase control circuits detect the presence or absence of stuff by one.
In such a case, N
In some cases, data in which stuff exceeding the stuff allowance specified by the NI system is inserted is transmitted to the opposite receiving device.

According to the provisions of the NNI system, stuffing is allowed only once in four consecutive frames, but stuffing is not allowed twice or more in four frames. If the stuff occurs twice or more in four frames, the receiving side cannot normally receive data.

FIG. 13 is a time chart of a conventional phase control circuit in the case where an abnormality occurs in which the stuff is considered to have occurred more than a specified number of times in the conventional example. In the figure, an abnormal state is shown in which normal stuff control for inserting invalid data of 3 bytes is performed for each frame. In the conventional phase control circuit, the number of bytes of the overhead part is determined for each frame. Since it is counted and compared with the threshold value 81 of the comparator, one of the input data
When it is determined that stuff occurs in a frame, the output data corresponding to that frame is always output under stuff control. Therefore, in such a case, the receiving device cannot receive the signal.

The present invention has been made in view of the above circumstances, and when a stuff is erroneously detected due to an abnormality in input data or the like, the stuff is performed a prescribed number of times in the NNI system, ie, one stuff per four frames. It is an object of the present invention to provide a phase control circuit for protecting the stuff control from exceeding the stuff control.

[0025]

FIG. 1 is a block diagram showing the basic configuration of the present invention. According to the present invention, in a phase control circuit for performing phase control of STM frame format data according to the NNI system input from a transmission device and outputting the data to a reception device, the phase control circuit synchronizes with the transmission clock input from the transmission device. Clock changing means 4 for changing the clock so that the data is synchronized with the receiving clock
And an information storage means 1 for storing the valid data part in the STM frame format, and monitoring that the valid data part is input, and generating an address of the information storage means 1 in which the valid data part is written. Writing control means 2 for sequentially writing the valid data portion to the generated address, and counting the number of bytes of the control data portion in the STM frame format over a period of eight frames, and then outputting the count value. An overhead counting means 5, a stuff control means 6 for detecting a stuff amount per eight frames for controlling a phase of data transmitted to the receiving device by comparing the count value with a predetermined threshold value, The phase of reading data is adjusted according to the amount of stuff, and the address of the information storage means 1 for reading the effective data portion is adjusted. Generates a scan, there is provided a phase control circuit, characterized in that a read control section 3 for sequentially reading control valid data portion stored in the generated address.

Here, the clock transfer means 4 is a known circuit comprising a flip-flop and a logic circuit such as AND or OR, and absorbs the phase difference between the transmission clock and the reception clock to synchronize with the reception clock. To generate input data.

The information storage means 1, for example a dual-port RAM and F IFO is used, it is capable of writing and reading of data at the same time by providing a write address and the read address. This is generally called a frame memory. The writing control means 2
It mainly comprises a counter for counting numerical values, and outputs a predetermined write address corresponding to the counted numerical value. The read control means 3 is composed of a counter for counting numerical values, and outputs a predetermined read address corresponding to the counted numerical values.

It is desirable that the overhead counting means 5 comprises a 1/8 frequency dividing circuit and a counter. Here, the １ ／ frequency divider circuit is configured by a flip-flop or a counter, extends the output period of the input signal by eight times, and sets the timing to be counted. Here, an operation for giving a start and an end of timing for counting the number of bytes of the control data portion over eight frames is performed.

The stuff control means 6 preferably comprises a comparator and a counter. The comparator is composed of a logic circuit such as AND or OR or a counter, compares the input count value with a threshold value stored in advance therein, and outputs a numerical value corresponding to the difference. .

[0030]

A transmission clock and NNI STM frame data synchronized with the transmission clock are input from the outside to the clock transfer means 4 of the present invention. A clock on the receiving side is also input to the clock changing means 4, and the clock changing means 4 performs a clock changing operation so that the data in the STM frame format is synchronized with the receiving clock.

[0031] Form-out write control unit 2, generates an address for one monitors whether valid data unit is input, writing the valid data portion into the information storage means 1 of the input data of the STM frame format I do. Thus, the valid data portion is sequentially written to the generated address.

The overhead counting means 5 includes the STM
After counting the number of bytes of the control data section in the frame format over a period of 8 frames, the count value is output.

Next, the stuff control means 6 detects the amount of stuff per eight frames for controlling the phase of data transmitted to the receiving device by comparing the count value with a predetermined threshold value.

The read control unit 3 adjusts the phase of reading data in accordance with the detected stuff amount, generates an address of the information storage unit 1 for reading the valid data portion, and stores the address in the generated address. Read the valid data section.

As described above, according to the present invention, the control data portion per 8 frames in the input data in the STM frame format is counted, and the counted value is compared with a predetermined threshold value to compare 8 frames. Per staff amount,
Data read control is controlled in accordance with this stuff amount.
Since the operation is performed in units of frames, the phase of output data can be changed according to the change in the phase of input data. Also, when input data is abnormal, erroneous staff detection is automatically canceled in units of 8 frames. To be
It is possible to prevent stuff control exceeding the specified number of stuffs of the NNI method, that is, stuff control exceeding one stuffing per four frames, and to output data according to the NNI method.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. Note that the present invention is not limited to this. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. Here, the frame synchronization section 29 has the same configuration as that described in the conventional example.

[0037] The frame synchronization unit 2 9, to detect and analyze the input data of the STM frame format, find the head position of the payload data is valid data in the STM frame to determine whether the staff. As shown in the figure, the frame synchronization unit 29 includes a payload information signal that outputs an “H” level during a period in which the payload data is input in synchronization with the payload data, and an overhead data (SOH).
Data signal), and generates an overhead information (SOH information) signal that outputs an “H” level during a period in which the SOH data is input.

Further, the frame synchronizer 29 generates a pointer pulse signal indicating the pointer start position, that is, the pointer point in the fourth row of the STM frame shown in FIG. The payload information signal, the SOH information signal, and the pointer pulse signal generated by the frame synchronization section 29 are input to the bit buffer 24 of the phase control circuit of the present invention.

The bit buffer 24 is a so-called clock transfer means for absorbing the phase difference between the transmission clock and the reception clock and outputting the payload data input from the frame synchronization section 29 in synchronization with the reception clock. It is. The transmission clock is a clock input from the transmission device side together with the input data, and the reception clock is a clock serving as a reference for transmitting the input data to the reception device, and is generated by the phase control circuit. Or
Alternatively, a clock sent from the receiving device is used.

In general, when the data of the STM frame is output from the transmitting device and when the clock is switched by the bit buffer 24, stuff control for adjusting the timing of the output data is performed.

Although each stuff control is performed not more than once in four frames in accordance with the provisions of the NNI system, the stuff control in the transmission device and the stuff control in the bit buffer 24 are performed independently of each other. ,
Both may occur simultaneously during any four frames,
In this case, stuffing occurs twice in four frames. However, during the next three frames, N
Because there is no staff in the NI standard,
No stuffing occurs more than twice in eight frames. Therefore, the presence or absence of the stuff may be detected in units of eight frames. If the stuff is detected more than twice in eight frames, it is treated as abnormal.

The payload counter 22 generates an address for writing the payload data to the frame memory 21. The payload counter 22 is initially set by a pointer pulse signal input through the bit buffer 24, and is enabled during an “H” level output period of payload information indicating that payload data is being input.

By counting the clocks on the receiving side during that time, addresses to be written in order from the data at the pointer point indicating the head of the payload data are given to the frame memory 21. Through the above operation, the payload data is sequentially written to a predetermined address of the frame memory 21. Here, the frame memory 21 is a RAM such as a dual-port memory, and is a memory from which reading and writing can be performed through another port.

The 1/8 frequency divider 25 and the overhead (O
H) The counter 26 constitutes overhead counting means for counting the number of bytes of the overhead part in the STM frame. The ８ frequency dividing circuit 25 receives the pointer pulse signal, generates timing for eight frames, and gives an instruction to the overhead counter 26 to start counting for eight frames.

After the overhead counter 26 is instructed to start counting by the ８ frequency dividing circuit 25,
During the input period of the overhead data indicated by the OH information signal, the number of receiving-side clocks is counted.
That is, the overhead counter 26 counts the number of bytes of overhead (SOH) data over eight frames while the SOH information signal is at the “H” level.

For example, as shown in FIG. 3, when there is no stuff, the STM frame is composed of 9 bytes of SOH data per line during one frame period.
× 9 rows = 81 (bytes) are counted, and 81 × 8 = 648 (bytes) are counted in the eight frame period.

S counted over the eight frames
The count value of the number of bytes of the OH data is sent to the comparator 27 and compared with a predetermined threshold value Th “648”. FIG.
As shown in FIG. 1, when there is no stuff, the count value output from the overhead counter 26 is 648, which is equal to the threshold value Th. Output from

The output value "0" from the comparator 27 is given to the stuff counter 28. This output value is a decoded signal of the detected stuff amount.
8 determines the output period of the inhibit signal output from the control signal 8. The stuff counter 28 supplies the frame counter 23 with an inhibit signal for instructing the timing of reading the payload data from the frame memory 21.

Since the period during which the stuff control is performed with the SOH data is the timing at which the payload data must not be read, the inhibit signal indicates the timing at which the payload data is to be read and the timing at which the payload data is not to be read. It is. For example, as shown in FIG. 3, when there is no stuff, the inhibit signal is output at "L" level only for a period of 9 bytes corresponding to SOH data, and is set to "H" for a period of 261 bytes corresponding to payload data. The level is output.

The inhibit signal is input as an enable signal of the frame counter 23, and the frame counter 23 counts the clock on the receiving side during the enable period and gives a predetermined read address to the frame memory 21. Thereby, the frame memory 21
The payload data written to the predetermined address is sequentially read in synchronization with the clock on the receiving side, and further loaded with the payload data at a predetermined timing position of the STM frame.

The above is an example of the operation when there is no stuff. When there is stuff, the count value of the overhead counter 26 is different, whereby the read timing of the payload data, that is, the phase is changed.
FIGS. 4 and 6 show examples in the case where the staff is present.

FIG. 4 shows an example in which the first frame to the seventh frame have no stuff and the eighth frame performs the normal stuff control, that is, the stuff control for the payload portion for 3 bytes.

Here, a 3-byte stuff occurs at the end of the eighth frame, and when there is no stuff, the counter value of the overhead counter 26 is 639.
Should be SO long by 3 bytes of staff
This indicates that the H information signal has been output and the count value of the overhead counter 26 has reached 642. At this time, when the counting of eight frames is completed, the overhead counter 26 sets the SOH count value to 64.
8 + 3 = 651 is output and input to the comparator 27.

In the illustration of the stuff operation shown in FIG. 6, (a) and (b) correspond to the stuff control of FIG. That is, when there is no stuff, the payload data is stored in the 3 bytes immediately after the SOH section, and (b)
The generation position of the pointer pulse signal indicated by 線 should be the position before the stuff indicated by the dotted line. However, when 3 bytes of stuff are generated, invalid data corresponding to the stuff is stored in 3 bytes immediately after the SOH section. Since the data is inserted and the head position of the payload data is the fourth byte and thereafter, the generation position of the pointer pulse signal is delayed by the stuff of 3 bytes.

The occurrence of the stuff is detected by the frame synchronizing unit 29, and in addition to the pointer pulse signal, the payload synchronizing signal and the SOH information signal are generated by the frame synchronizing unit 29 according to the amount of the stuff. Is done. For example, FFH is used as the 3-byte invalid data inserted by the stuff.

As described above, when the stuff is generated as shown in FIGS. 4 and 6A, the comparator 2
In step 7, the input counter value "651" is compared with a predetermined threshold value "648", and the value of "+3" is supplied from the comparator 27 to the stuff counter 28 as a stuff decode signal.

When the numerical value of “+3” is input, the stuff counter 28 stores the value of 3 inserted by the stuff control.
An inhibit signal is transmitted such that the overhead part is extended for a period corresponding to the invalid data of the byte.

Next, the frame counter 23 which receives the inhibit signal as an enable signal inhibits reading of data for 9 + 3 = 12 bytes corresponding to the overhead portion, and reads 258 bytes of payload data at the subsequent timing. Then, the read address is output to the frame memory 21.

As described above, in the case where the stuff occurs once as shown in FIG. 4 during the data input period of eight frames, the count value of the overhead counter 26 at the end of the eight frame period is 468 + 3 = 45
The decoded signal of "+3" is supplied from the comparator 27 to the stuff counter 28 so that the stuff is generated once during the data output period of the next four frames.

That is, instead of detecting the presence / absence of stuff for each frame and controlling the stuff on the reading side as in the prior art, the amount of stuff is detected over eight frames and input of eight frames is performed. Since the read-side stuff is controlled after receiving the data, even if the input data is abnormal, erroneous detection of the stuff is canceled and the stuff amount data according to the NNI method can be output.

FIGS. 6 (c) and 6 (d) show a case where a stuff is inserted in the 3-byte stuff area of the overhead part such that valid data is inserted. In this example, since the payload data, which is valid data, has increased by 3 bytes and the overhead data has decreased by 3 bytes, the pointer points to the head position of the payload data as shown in FIGS. Shifts to the overhead part by 3 bytes, and the generation position of the pointer pulse signal is 3 bytes.
Faster by bytes.

Therefore, the SOH information signal input to the overhead counter 26 is shorter by 3 bytes, and the output counter value is 648-3 = 6 at the end of the 8 frame period.
45 is output.

In the comparator 27, at the end of the eight frame period, the input count value “645” and the threshold value T
h "648" is compared, a "-3" decoded signal is sent to the stuff counter 28, and during the data output period of the next four frames, an inhibit signal whose overhead part is reduced by 3 bytes is sent to the stuff counter 28. 28 to the frame counter 23.

In the NNI system, one out of four frames
Since two stuffs are allowed, two stuffs may be detected in eight frames monitored by the overhead counter 26. However, as shown in FIG.
When the stuff to the side occurs twice, the output counter value of the overhead counter 26 is 648 + 3 + 3.
= 654, and the comparator 27 outputs a decode signal of “+6”.

Then, an inhibit signal is output from the stuff counter 28 and the payload data is read out so that one stuff is performed in the next four frame periods and one stuff is performed in the next four frame periods. It is.

When the negative stuff occurs twice in eight frames as shown in FIG. 6C, the output counter value of the overhead counter 26 becomes 648-3-.
3 = 642, and the comparator 27 outputs a decoded signal of “−6”, and the stuff counter 28 performs stuffing once in the next four frame periods and further in the next four frame periods. Outputs an inhibit signal.

As described above, when the stuff occurs once or twice during the period of eight frames of the input data, the stuff control corresponding to each stuff amount is performed on the reading side, and the data becomes normal. Is read in accordance with the NNI specification, but if an error occurs in the input data due to a transmission circuit error and it is considered that stuff exceeding the specification has occurred, the comparator 27 decodes “0”. Output a signal.

[0068] That is, or 8 frame Moore, when staff three or more is detected, is not performed stuff control the reading side, staff erroneous detection so as to cancel at 8 frames . This makes it possible to output payload data in accordance with the NNI standard.

FIG. 5 shows that during eight frames of input data,
FIG. 6A shows a case where the stuff of FIG. 6A is generated for each frame. At the end of the eight frame period,
The count value output from the overhead counter 26 is 648 + 24 = 672.
The comparison result with the threshold value Th = 648 is +24.

However, since it does not match any of the stuff controllable values ± 3 and ± 6 during the eight frame period, the stuff is considered to be abnormal and the output value of the comparator 27 is set to " 0 "is output.

As described above, by detecting a change in the stuff amount of input data in units of eight frames, the phase on the read side can be adjusted in response to a change in the position of valid data of the input data, that is, a change in phase. Thus, even if the stuff is erroneously detected, it is possible to output data according to the NNI standard.

[0072]

According to the present invention, the control data portion per 8 frames in the input data in the STM frame format is counted, and this count value is compared with a predetermined threshold value to compare the control data portion per 8 frames. Since the stuff amount is detected and the data reading control is performed in units of eight frames in accordance with the stuff amount, the phase of the output data can be changed in accordance with the change in the phase of the input data.
In addition, even when the input data is abnormal, the erroneous detection of the stuff is automatically canceled in units of eight frames, so that the stuff control exceeding the specified number of stuffs of the NNI system, that is, the stuff control exceeding one stuffing per four frames can be prevented. ,
Data according to the NNI method can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a time tie chart in a case where there is no staff in one embodiment of the present invention.

FIG. 4 is a time chart when a staff is generated according to the embodiment of the present invention.

FIG. 5 is a time chart in the case of a staff detection abnormality in one embodiment of the present invention.

FIG. 6 is an explanatory diagram of a stuff operation in one embodiment of the present invention.

FIG. 7 is an explanatory diagram of a format configuration of an STM frame.

FIG. 8 is an explanatory diagram of a configuration of an STM frame developed on a time axis.

FIG. 9 is a block diagram showing a conventional system configuration.

FIG. 10 is a configuration block diagram of a phase control circuit in a conventional example.

FIG. 11 is a time chart when there is no staff in the conventional example.

FIG. 12 is a time chart when a staff member occurs in the conventional example.

FIG. 13 is a time chart in the case where stuff detection is performed for each frame in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Information storage means 2 Write control means 3 Read control means 4 Clock transfer means 5 Overhead (OH) counting means 6 Stuff control means 21 Frame memory 22 Payload counter 23 Frame counter 24 Bit buffer 25 1/8 frequency divider 26 Overhead (OH) ) Counter 27 Comparator 28 Stuff counter 29 Frame synchronization unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-30098 (JP, A) JP-A-6-6331 (JP, A) JP-A 1-293032 (JP, A) JP-A-3-300 278734 (JP, A) JP-A-4-220827 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 5/22-5/26 H04L 7/00-7/10

Claims (1)

(57) [Claims] 1. A phase control circuit for controlling the phase of STM frame data according to an NNI system input from a transmission device and outputting the data to a reception device, wherein the phase control circuit synchronizes with a transmission clock input from the transmission device. Clock changing means (4) for changing the clock so that the input data is synchronized with the clock on the receiving side, and information storage means (1) for storing the effective data portion in the STM frame format
Monitor that the valid data portion is input, generate an address of the information storage means (1) to which the valid data portion is written, and control to sequentially write the valid data portion to the generated address. Writing control means (2)
Overhead counting means for counting the number of bytes of the control data portion in the STM frame format over a period of eight frames and outputting the count value (5)
A stuff control means (6) for detecting a stuff amount per eight frames for controlling a phase of data transmitted to the receiving device by comparing the count value with a predetermined threshold value; A read control for adjusting a phase of reading data in accordance with the above, generating an address of the information storage means (1) for reading the valid data portion, and sequentially reading the valid data portion stored at the generated address. A phase control circuit, comprising: