JPH06165265A - Remote supervisory and controlling equipment - Google Patents

Abstract

PURPOSE:To provide a remote supervisory and controlling equipment provided with a highly accurate time function even when the bit length of time data fluctuates. CONSTITUTION:This remote supervisory and controlling equipment for transmitting the frames of a high level data link control procedure format from a control center unit which is a time transmission station to a center unit to be controlled which is a time reception station and performing the time synchronization of the time transmission station and the time reception station is provided with a data discrimination circuit 1 for discriminating whether or not a dummy bit for discriminating a flag is inserted to the time data of the frame and generating a pulse every time when the dummy bit is inserted, a counter 2 for counting the pulses and measuring the number of times when the dummy bit is inserted and a CPU 9 for performing time correction based on the transmission delay fixed errors of the time transmission station 3 and the time reception station 6 and the number of times when the dummy bit is inserted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives time data transmitted from a time transmitting station, which is a control station device, at a time receiving station, which is a controlled station device, and corrects the time at the received time receiving station. The present invention relates to a remote monitoring control device having a time synchronization function.

[0002]

2. Description of the Related Art Generally, a distant monitoring control device is composed of a control station device and a controlled station device, and monitors and controls equipment at a remote electric station such as a power station or a substation from a central monitoring station. It has become. Main functions of such a distant monitoring control device include a control function for a controlled station to be monitored and controlled, a display function for displaying the state of the controlled station, and a measurement function. The conventional remote monitoring and control device monitors and controls only one electric station, and the control station device and the controlled station device have a small-scale configuration that corresponds to 1: 1. In recent years, however, the power system has expanded. Accordingly, it has become necessary to perform a large-scale, centralized supervisory control of 1: N type, which has a function of connecting to a computer and in which one controlled station device and N controlled station devices face each other.

When a power system accident is considered, for example, if the circuit breaker at the controlled station A trips and the circuit breaker at another controlled station B trips, the circuit breaker at the controlled station A trips. Later, the cause of the accident will change depending on whether the circuit breaker at another controlled station B trips or vice versa. In such a case, the time at which the circuit breaker trips from each controlled station and the trip information are sent to the control station device, and the information from each controlled station is rearranged in the control station device in chronological order. Accident analysis needs to be done.

Therefore, it is necessary to grasp the order of trips, and it is necessary to set the clocks of each controlled station, for example, a substation. Therefore, conventionally, the clock of the time transmitting station (for example, the control station device) is added to the time receiving station (for example, the controlled station device).
The method of adjusting the clock of is considered.

FIG. 5 shows an example of data transmission in the conventional time synchronization. The time transmitting station transmits time data at time T1 shown in FIG. 5, and the time receiving station completes reception of time data at time T2. Therefore, in both stations, T2-T1
There is a delay time. This delay time is a delay time mainly due to the modem, the transmission path, and the transmission frame length, and since it can be generally grasped as a fixed value, it is corrected on the time receiving station side.

[Problems to be Solved by the Invention]

However, the transmission unit (frame) of the transmission system HDLC (High Level Data Link Control Procedure Format) has a structure as shown in FIG. 3, and there are 8-bit flags before and after the frame. In HDLC (High Level Data Link Control Procedure Format), in order to compensate for transparency, if the number of consecutive bits '1' is 5 so that the same bit pattern as the flag does not appear in positions other than the flag, the dummy bit is set on the transmitting side. '0' is inserted (Fig. 4
reference). Therefore, when the bit “0” is inserted in the time data, even if the time data is transmitted from the time transmitting station at the time T1, the reception of the time data is delayed until time T2 + Δ. Therefore, in addition to the delay time of T2-T1 (fixed error), an error of Δ time also occurs. Therefore, the transmission time (T1) and the reception time (T2)
Fluctuates, which greatly affects the accuracy of time synchronization.

For example, assuming that there are a total of n '0' insertions and the transmission rate is 1200 bps, a maximum of about 0.
The delay is 83 × 0 milliseconds (n / 1200 bps × 10 milliseconds). In recent years, in a distant monitoring and control device that requires an accuracy of a time error of 1 millisecond or less, this error is large and has been a problem.

An object of the present invention is to provide a distant monitoring control apparatus having a highly accurate time function even if the bit length of time data changes.

[0009]

A distant monitoring control device of the present invention transmits a frame of a high level data link control procedure format from a control station device which is a time transmitting station to a controlled station device which is a time receiving station, A distant monitoring control device that performs time synchronization between a time transmitting station and a time receiving station, and determines whether a dummy bit for identifying a flag is inserted in the time data of a frame and when the dummy bit is inserted Is a data discrimination circuit that generates a pulse each time, a counter that counts the pulse and measures the number of times the dummy bit is inserted, a fixed transmission delay error between the time transmitting station and the time receiving station, and the number of times the dummy bit is inserted. And a CPU for performing time correction based on the above.

[0010]

As a result, the data discriminating circuit of the time receiving station discriminates whether or not there is a 0 insertion in the time data, and corrects the time data based on the number of 0 insertions.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a remote monitoring and control apparatus of the present invention. The difference from the conventional distant monitoring control device is that a data discriminating circuit 1 and a counter 2 are added.

In FIG. 1, when data communication is performed, data (DC signal) sent from the transmission circuit 4 on the time transmitting station 3 side is once modulated into an AC signal (modulation is performed through the modem 5). Time to send and receive Receiving station 6
To the side, the AC signal is again modulated into a DC signal and the modulated signal is transmitted through the modem 7. The signal sent to the receiving circuit 8 is converted into serial and parallel signals, and CP
Data is exchanged with U9, and the other signal is sent to the data discriminating circuit 1. A flow chart of the data discriminating circuit is shown in FIG. The data discriminating circuit 1 performs the counter up by the counter 2 when it receives 5 consecutive bits of “1” and then receives 0 during data reception.
However, when 6-bit continuous 1 is received, the data is a flag, and therefore the count-up is not performed. When the data transmission is completed (the data discriminating circuit 1 receives the flag), the data discriminating circuit 1 outputs a counter stop signal for the counter 2.

Since the value of the counter 2 represents the number of zero insertions, (the number) * (1 bit transmission time) corresponds to the Δ time in FIG. By providing this time as a correction value for the time setting in the time receiving station 3, accurate time synchronization becomes possible.

Next, FIG. 2 shows the operation of the data discriminating circuit 1. During data reception, 5 consecutive bits of 1 are received,
Further, when 0 is received next time, the counter 2 counts up. However, when 6-bit continuous 1 is received, the data means a flag, and therefore the count-up is not performed. When the data transmission ends (the receiving circuit receives the flag), the time receiving side corrects the delay time (fixed error) of the data reception at the time T1 shown in FIG. 5 and the transmission of T2-T1. The data discriminating circuit stops the counter value.

Further, the receiving circuit 8 to the CPU 9 shown in FIG.
The CPU 9 reads the value of the counter 2 stopped by the data discriminating circuit 1 by the reception completion interrupt. After that, the value of the counter 2 is reset by the reset command from the CPU 9, and the state of waiting for the next data input is entered. The CPU 9 sets the value of the counter 2 to a natural number (1, 2,
3) indicates that a 0 was inserted during the data reception, and the CPU 9 causes the data discriminating circuit 1 to correct the time data by inserting the 0 (receive the 0 inserted by the transmitting side). It should be removed on the side.), So there is no time error. When the CPU 9 reads the value of the counter 2 as 0, it indicates that 0 has not been inserted. Therefore, no time error occurs and it is not necessary to correct the time data by inserting 0.

Further, in FIG. 1, it is also possible to perform processing by changing the signal output from the data discriminating circuit 1 to one signal which counts up only during data reception. When the data transmission is completed (the receiving circuit receives the flag), the time receiving station side receives the data (T1) shown in FIG. 5 and corrects the delay time (fixed error) of the transmission of T2-T1. The data discriminating circuit 1 stops the value of the counter 2. In addition, the reception completion interrupt from the reception circuit 8 to the CPU 9 shown in FIG.
9 is a counter 2 stopped by the data discrimination circuit 1
Come read the value of. After that, the value of the counter 2 is the CPU 9
It is reset by the reset command from and enters the state of waiting for the next data input.

The CPU 9 sets the value of the counter 2 to a natural number (1,
If it is read as 2, 3 ,,), during data reception,
This indicates that 0 has been inserted, and the CPU 9 causes the data discriminating circuit 1 to correct the time data by inserting 0 (remove the 0 inserted on the transmitting side on the receiving side). ], There is no time error. When the CPU 9 reads the value of the counter 2 as 0, it indicates that 0 has not been inserted. Therefore, no time error occurs and it is not necessary to correct the time data by inserting 0.

[0018]

As described above, according to the present invention, even if a time error occurs due to the insertion of 0, by using the data discriminating circuit and the counter, the time error between the transmission time and the reception time (Fig. It is possible to provide a distant monitoring and control apparatus that performs time synchronization between the time transmitting station and the time receiving station with high accuracy without the error of Δ time shown in 5).

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the data discrimination circuit of the present invention.

FIG. 3 is an explanatory diagram of a transmission unit (frame) of a high level data link control procedure format.

FIG. 4 is an explanatory diagram of inserting a “0” bit for compensating for transparency.

FIG. 5 is an explanatory diagram of time data at a time transmitting station and a time receiving station.

[Explanation of symbols]

 1 Data Discrimination Circuit 2 Counter 3 Time Transmission Station 4 Transmission Station 5 Modem 6 Time Reception Station 7 Modem 8 Reception Circuit 9 CPU

Claims (1)

[Claims] 1. A control station device which is a time transmitting station transmits a frame of a high level data link control procedure format to a controlled station device which is a time receiving station to synchronize time between the time transmitting station and the time receiving station. In the distant monitoring control device to perform, it is determined whether or not a dummy bit for identifying a flag is inserted in the time data of the frame, and when the dummy bit is inserted, a data determination circuit that generates a pulse each time, and A counter that counts pulses and measures the number of times the dummy bit is inserted, and a CPU that performs time correction based on the fixed transmission delay error between the time transmitting station and the time receiving station and the number of times the dummy bit is inserted. And a remote monitoring and control device.