CN109254221A - A kind of data processing method of intelligent substation - Google Patents
A kind of data processing method of intelligent substation Download PDFInfo
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- CN109254221A CN109254221A CN201811417899.1A CN201811417899A CN109254221A CN 109254221 A CN109254221 A CN 109254221A CN 201811417899 A CN201811417899 A CN 201811417899A CN 109254221 A CN109254221 A CN 109254221A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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Abstract
The invention discloses a kind of data processing methods of intelligent substation, including receiving multi-channel sampling data by FPGA secondary processor and carrying out validity check processing to the sampled data, and the sampled data is ranked up and sampling instant synchronization process when sampled data verification is effective；And carry out logic discrimination processing；Wherein, the sampled data includes two-way sample rate current, measures electric current all the way and measures voltage all the way；The data that FPGA secondary processor processing is completed are sent to relevant transformer equipment by ARM primary processor.The data processing method makes full use of FPGA secondary processor I/O interface abundant and quick parallel processing speeds and the efficient data-handling capacity of ARM primary processor, with faster operation speed, signal processing duration can be effectively reduced, signal is improved and transmits timeliness.
Description
Technical field
The present invention relates to intelligent substation field, in particular to a kind of data processing method of intelligent substation.
Background technique
Intelligent substation realizes whole station information digitalization, communications platform networking and information sharing mark using smart machine
Standardization is the key node of smart grid.Combining unit is the base support equipment of intelligent substation, for realizing electric system
The information digitalization of Current Voltage.Existing combining unit completes every operation and communication using uniprocessor, signal processing with
Transmission process causes longer delay, causes adverse effect to the timeliness of signal transmission.In addition, compared with conventional substation,
The ratio of defects of the relevant devices such as the protective device of intelligent substation is higher, especially most with combining unit, and proportion is more than half,
Seriously affect the normal operation of intelligent substation.
Therefore, the arithmetic speed of combining unit how is improved, signal processing duration is reduced, improving signal transmission timeliness is
Those skilled in the art's technical problem urgently to be resolved.
Summary of the invention
The object of the present invention is to provide a kind of data processing methods of intelligent substation, can effectively improve the fortune of combining unit
Speed is calculated, signal processing duration can be reduced, signal is improved and transmits timeliness.
In order to solve the above technical problems, the present invention provides a kind of data processing methods of intelligent substation, comprising:
Multi-channel sampling data are received by FPGA secondary processor and validity check processing is carried out to the sampled data,
And the sampled data is ranked up and sampling instant synchronization process when sampled data verification is effective；And it is patrolled
Collect differentiation processing；Wherein, the sampled data includes two-way sample rate current, measures electric current all the way and measures voltage all the way；
The data that FPGA secondary processor processing is completed relevant power transformation is sent to by ARM primary processor to set
It is standby.
Optionally, validity check is carried out to the sample rate current by the FPGA secondary processor, comprising:
It makes the difference the two-way sample rate current to obtain current differential；
Compare the size of the current differential and preset threshold；
If the current differential is less than the preset threshold, the sample rate current is effective.
Optionally, further includes:
If the sample rate current, which verifies invalid number, reaches preset value, the FPGA secondary processor will be corresponding remote
The status indicator of end equipment is operation irregularity.
Optionally, the FPGA secondary processor is ranked up the sampled data, comprising:
Fifo queue is written into the sampled data according to preset order, and correlating markings position is set.
Optionally, further includes:
If not receiving one or more sampled data within the default waiting time, the FPGA processor is by institute
It states the corresponding sampled data in fifo queue and is written as zero.
Optionally, the FPGA secondary processor carries out sampling instant synchronization process to the sampled data, comprising:
Synchronization signal is received, is adopted by the sampling data synchronization that difference arithmetic sends different acquisition device to identical
The sample moment；
The sampled data that each collector of different combining units is sent is received, and is judging rising for the sampled data
Beginning frame generates corresponding markers when correct；After completing sampled data reception, the sampled data and the markers are sent to
The ARM primary processor, so that the ARM primary processor obtains sampling time delay according to the markers and prolonged according to the sampling
When, realize that sampling instant is synchronous by phase compensation.
Optionally, further includes:
If the synchronization signal failure, the FPGA secondary processor starts internal crystal oscillator frequency dividing and generates lock-out pulse,
And alarm signal is sent to secondary device.
Optionally, the FPGA secondary processor carries out logic discrimination, comprising:
The GOOSE information of relevant device is obtained by process bus；
Analyze the GOOSE information, according to logic of propositions differentiate mechanism carry out voltage side by side with switching.
The data processing method of intelligent substation provided by the present invention, including multichannel is received by FPGA secondary processor
Sampled data simultaneously carries out validity check processing to the sampled data, and adopts when sampled data verification is effective to described
Sample data are ranked up and sampling instant synchronization process；And carry out logic discrimination processing；Wherein, the sampled data includes two
Road sample rate current measures electric current all the way and measures voltage all the way；It will be at the FPGA secondary processor by ARM primary processor
The data that reason is completed are sent to relevant transformer equipment.
It is compared to the conventional solution that operation and communication are completed by uniprocessor, at data provided by the present invention
Reason method, using the master-slave mode processor architecture of FPGA secondary processor and ARM primary processor, by FPGA secondary processor into
Row data receiver, verification, sample-synchronous and logic discrimination processing realize data transmission by ARM primary processor.At the data
Reason method makes full use of FPGA secondary processor I/O interface abundant and quick parallel processing speeds and ARM primary processor
Efficient data-handling capacity.Arithmetic speed can be effectively improved, signal processing duration is reduced, signal is improved and transmits timeliness.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of flow diagram of the data processing method of intelligent substation provided by the embodiment of the present invention.
Specific embodiment
Core of the invention is to provide a kind of data processing method of intelligent substation, can effectively improve arithmetic speed, energy
Signal processing duration is enough reduced, signal is improved and transmits timeliness.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to FIG. 1, Fig. 1 is a kind of process of the data processing method of intelligent substation provided by the embodiment of the present invention
Schematic diagram；With reference to Fig. 1 it is found that the data processing method includes:
S100: receive multi-channel sampling data and right by FPGA secondary processor: sampled data carries out at validity check
Reason, and sampled data is ranked up and sampling instant synchronization process when sampled data verification is effective；And it carries out logic and sentences
Other places reason；Wherein, sampled data includes two-way sample rate current, measures electric current all the way and measures voltage all the way；
Specifically, FPGA secondary processor is placed in ARM primary processor front end, the multi-channel sampling number that collector is sent is received
According to, including two-way sample rate current, electric current is measured all the way and measures voltage all the way；The road Bing Duige sampled data carries out validity school
Processing is tested, including cyclic redundancy check is carried out to each road sampled data, and sampled value validity check is carried out to sample rate current.
And when sampled data is effective, sampled data is ranked up and sampling instant synchronization process；And carry out logic discrimination processing.
Specifically, multi-channel sampling data can be received by the data reception module of FPGA secondary processor and to hits
According to progress validity check processing, and sampled data is ranked up when sampled data is effective；When sampled data is effective, lead to
The synchronous processing module for crossing FPGA secondary processor carries out sampling instant synchronization process to sampled data；And FPGA can be passed through
The logic discrimination module of secondary processor carries out logic discrimination processing.By modularized design, combining unit can be effectively improved
Stability and dependability, while convenient for operation management and maintenance.
In a kind of specific embodiment, carrying out validity check to sample rate current by FPGA secondary processor can be with
It include: to make the difference two-way sample rate current to obtain current differential；Compare the size of the current differential and preset threshold；If current differential
Less than preset threshold, then sample rate current is effective.
Specifically, the gain having the same of two-way analog channel and element, analog signal therein pass through after A/D is sampled
Optical fiber is transmitted to FPGA secondary processor.The size of FPGA secondary processor real-time judge two-way sample rate current obtains having for the two
Effect property.Specifically two-way sample rate current is made the difference to obtain the current differential of the two, and further compares the current differential and default threshold
The size of value can take first the absolute value of the current differential, and then judge whether the absolute value is less than preset threshold, if being less than,
Then sample rate current is effective, and remote equipment is working properly；On the contrary, sample rate current is invalid if being not less than, remote equipment is abnormal.
Wherein, for the specific value of above-mentioned preset threshold, the present invention does not do unique restriction, can according to actual needs into
The setting of row otherness.
Further, optionally, it if can also include: that sample rate current verifies invalid number and reaches preset value, will correspond to
Remote equipment status indicator be operation irregularity.
Specifically, remind staff to carry out equipment replacement in time to reach, to ensure the normal operation of intelligent substation,
FPGA secondary processor can also continue more line in the current differential of two-way sample rate current, i.e. sample rate current verifies invalid number
It is operation irregularity by the status indicator of corresponding remote equipment when reaching preset value, to prompt staff's remote equipment to exist
Failure.
Equally, for the size of above-mentioned preset value, the present invention is not specifically limited, can be suitable in conjunction with actual conditions setting
Numerical value.
In addition, optional, it may include: that will adopt according to preset order that FPGA secondary processor, which is ranked up sampled data,
Fifo queue is written in sample data, and correlating markings position is arranged.
Specifically, mutually indepedent when different data channel transmission data, each road sampled data reaches the successive of combining unit
And be not fixed, it then, further can also be according to after FPGA secondary processor receives each road sampled data and carries out validity check
Fifo queue is written into each road sampled data according to preset order, and corresponding flag bit is set, to indicate that the sampled data continues
It takes.
Further, optionally, if can also include: not receive one or more hits within the default waiting time
According to sampled data corresponding in fifo queue is then written as zero.
Specifically, for the case where can not reaching combining unit there may be sampled data, in the present embodiment, FPGA auxiliary
Processor can also judge whether receive each road sampled data within the default waiting time, if presetting in the waiting time not at this
One or more sampled data is received, then the road sampled data corresponding in fifo queue is written as zero.It further can be with
Alarm is issued, to indicate corresponding data channel failure.
Optionally, it may include: to receive to synchronize that FPGA secondary processor, which carries out sampling instant synchronization process to sampled data,
Signal, the sampling data synchronization sent different acquisition device by difference arithmetic to identical sampling instant；Receive different merging
The sampled data that each collector of unit is sent, and corresponding markers is generated when the start frame for judging sampled data is correct；When
After completing sampled data reception, sampled data and markers are sent to ARM primary processor, so that ARM primary processor is according to markers
It obtains sampling time delay and according to sampling time delay, passes through phase compensation and realize sampling instant synchronization process.
Specifically, multi-channel sampling data are synchronized to identical sampling instant by FPGA secondary processor, so that it is guaranteed that supply
The current or voltage data of secondary device are consistent in timing.Specifically include synchronization process between different samplers and different merging
Synchronization process between unit.For the former, FPGA secondary processor can be according to synchronization signal, by difference arithmetic by different acquisition
The sampling data synchronization that device is sent is to identical sampling instant.For the latter, FPGA secondary processor receives different combining units
The sampled data that sends of each collector, and corresponding markers is generated when the start frame for judging sampled data is correct；Work as completion
After sampled data is received and synchronized using above-mentioned difference arithmetic progress difference, sampled data and markers are sent to ARM master
Processor.To which, ARM primary processor according to markers obtains sampling time delay and further according to sampling time delay, pass through phase compensation
Realize that sampling instant is synchronous.For the specific implementation process of difference arithmetic and phase compensation, referring to the prior art, this hair
It is bright not repeat them here.
Further, optionally, if can also include: synchronization signal failure, start internal crystal oscillator frequency dividing and generate synchronous arteries and veins
Punching, and alarm signal is sent to secondary device.
Specifically, when synchronization signal failure, FPGA secondary processor can also open to ensure that synchronization process can be realized
Dynamic internal crystal oscillator frequency dividing generates lock-out pulse, and sends alarm signal to secondary device.
Optionally, it may include: to obtain relevant device by process bus that FPGA secondary processor, which carries out logic discrimination,
GOOSE information；Analyze the GOOSE information, according to logic of propositions differentiate mechanism carry out voltage side by side with switching.
Specifically, FPGA secondary processor can obtain relevant device by process bus, such as breaker, disconnecting link state
GOOSE information, and the GOOSE information is analyzed, it is suitable to select according to logic of propositions differentiation mechanism progress voltage side by side with switching
The voltage of bus electronic type voltage transformer is sent to the intelligent electronic devices such as the protection, observing and controlling, calculating of wall, and is occurring
It sends a warning message when failure.
S200: the data that the processing of FPGA secondary processor is completed are sent to by relevant power transformation by ARM primary processor and are set
It is standby.
Specifically, ARM primary processor is mainly used for data transmission, it specifically can be by data transmission blocks therein by front end
The data completed of FPGA secondary processor processing, carry out according to communication protocol as defined in IEC61850-9-2 standard using data
Unit framing, and issued in real time by Ethernet to relevant transformer equipment.Wherein, above-mentioned transformer equipment can be protection dress
It sets, bus differential protection device, measure and control device etc., to realize that more devices of sampled data are shared.Further, it is also possible to pass through wireless network
Network is transmitted to Ling Jin substation, to realize multi-party shared and emergency the emergency cooperative of data.
In conclusion the data processing method of intelligent substation provided by the present invention, using FPGA secondary processor with
The master-slave mode processor architecture of ARM primary processor, by FPGA secondary processor carry out data receiver, verification, sample-synchronous with
And logic discrimination processing, data transmission is realized by ARM primary processor.FPGA secondary processor I/O abundant is made full use of to connect
The characteristics of mouth and quick parallel processing speeds and the efficient data-handling capacity of ARM primary processor.Operation can be effectively improved
Speed reduces signal processing duration, improves signal and transmits timeliness.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.
The data processing method of intelligent substation provided by the present invention is described in detail above.It is used herein
A specific example illustrates the principle and implementation of the invention, and the above embodiments are only used to help understand
Method and its core concept of the invention.It should be pointed out that for those skilled in the art, not departing from this
, can be with several improvements and modifications are made to the present invention under the premise of inventive principle, these improvement and modification also fall into the present invention
Scope of protection of the claims.
Claims (8)
1. a kind of data processing method of intelligent substation characterized by comprising
Multi-channel sampling data are received by FPGA secondary processor and validity check processing is carried out to the sampled data, and are worked as
The sampled data is ranked up when verifying effective to the sampled data and sampling instant synchronization process；And it carries out logic and sentences
Other places reason；Wherein, the sampled data includes two-way sample rate current, measures electric current all the way and measures voltage all the way；
The data that FPGA secondary processor processing is completed are sent to relevant transformer equipment by ARM primary processor.
2. data processing method according to claim 1, which is characterized in that by the FPGA secondary processor to described
Sample rate current carries out validity check, comprising:
It makes the difference the two-way sample rate current to obtain current differential；
Compare the size of the current differential and preset threshold；
If the current differential is less than the preset threshold, the sample rate current is effective.
3. data processing method according to claim 2, which is characterized in that further include:
If the sample rate current, which verifies invalid number, reaches preset value, the FPGA secondary processor sets corresponding distal end
Standby status indicator is operation irregularity.
4. data processing method according to claim 3, which is characterized in that the FPGA secondary processor is to the sampling
Data are ranked up, comprising:
Fifo queue is written into the sampled data according to preset order, and correlating markings position is set.
5. data processing method according to claim 4, which is characterized in that further include:
If not receiving one or more sampled data within the default waiting time, the FPGA processor will be described
The corresponding sampled data is written as zero in fifo queue.
6. data processing method according to claim 5, which is characterized in that the FPGA secondary processor is to the sampling
Data carry out sampling instant synchronization process, comprising:
Synchronization signal is received, when the sampling data synchronization to the identical sampling for different acquisition device being sent by difference arithmetic
It carves；
The sampled data that each collector of different combining units is sent is received, and in the start frame for judging the sampled data
Corresponding markers is generated when correct；After completing sampled data reception, the sampled data and the markers are sent to described
ARM primary processor leads to so that the ARM primary processor according to the markers obtains sampling time delay and according to the sampling time delay
It crosses phase compensation and realizes that sampling instant is synchronous.
7. data processing method according to claim 6, which is characterized in that further include:
If the synchronization signal failure, the FPGA secondary processor starts internal crystal oscillator frequency dividing and generates lock-out pulse, concurrently
Send alarm signal to secondary device.
8. data processing method according to claim 7, which is characterized in that the FPGA secondary processor carries out logic and sentences
Not, comprising:
The GOOSE information of relevant device is obtained by process bus；
Analyze the GOOSE information, according to logic of propositions differentiate mechanism carry out voltage side by side with switching.
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| CN110967581A (en) * | 2019-11-27 | 2020-04-07 | 云南电网有限责任公司电力科学研究院 | Test system and method |
| CN112632127A (en) * | 2020-12-29 | 2021-04-09 | 国华卫星数据科技有限公司 | Data processing method for real-time data acquisition and time sequence of equipment operation |
| CN112988631A (en) * | 2019-12-16 | 2021-06-18 | 西安西电电力系统有限公司 | Data processing method and device based on field programmable gate array |
| CN113078977A (en) * | 2021-03-18 | 2021-07-06 | 国网江苏省电力有限公司常州供电分公司 | Data synchronization method, synchronization device and storage medium |
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Application publication date: 20190122 |
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