JP3019917B2 - High-speed FIFO circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (Firs
More particularly, the present invention relates to a high-speed FIFO circuit suitable for temporarily storing data that can be processed only at a low speed and outputting data in the order of high-speed processing.

[0002]

2. Description of the Related Art Usually, a FIFO circuit is used as a memory, and stored data can be read out in a writing order. Therefore, the FIFO circuit is connected between the high-speed operation data processor and the low-speed operation peripheral device,
It is used as a buffer memory when sending data from a data processor to a peripheral device.

Since the FIFO circuit has a limited storage capacity, stored data becomes full when the number of reads is smaller than the number of writes, and if writing is continued in this state, the data has not been read yet. New data may be written on the stored data. On the other hand, if the reading proceeds while the writing is interrupted, for example, the stored data once read may be read again.

[0004] In order to solve the above problems, F
When the memory is full with storage data, the IFO circuit generates full flag information to notify the data processor side and inhibit writing. On the other hand, if the stored data that has been written once has been read out, the empty flag (Empty Flat) is read.
g) Generate information and inhibit reading.

A circuit device having the above functions is described in, for example, JP-A-61-296424, which will be briefly described with reference to FIG.

Writing / reading (hereinafter abbreviated as W / R)
Controller 30 receives write and read commands from a data processor and peripherals (both not shown) to control writing and reading of memory 48, respectively. W /
R controller 30 sends write and read signals corresponding to write address ring counter 32 via write line 34 and to read address ring counter 36 via read line 38.

[0007] The comparator 40 is connected to the write address ring counter 32 and the read address ring counter 36 via a plurality of conductors 42 and 44. Comparator 4
0 is also connected to the W / R controller 30 by line 46, and the write and read address ring counters 32,
Signals when 36 indicates the same address. With this information, W / R controller 30 can determine when memory 48 is full or empty.

The memory 48 has a plurality of memory word registers 50-1 to 50-N which store words 1 to N.
Is stored. Each memory word register is connected to one stage of the write address ring counter 32 and performs a memory write operation of this memory word register. Further, each memory word register is also connected to an associated stage of read address ring counter 36 for performing a memory read operation. In the following description, the memory word location addressed during a write or read operation will be indicated by one of the ring counters 32 or 36. The read address ring counter 36 is the write address ring counter 3
2, the same memory word registers 50-1 to 50-
When N is indicated and the last memory operation was a write operation, the memory 48 is full.

Similarly, when the write and read address ring counters 32, 36 point to the same memory word registers 50-1 through 50-N, and when the last received command is a read command, memory 48 is Since it is empty, even if a subsequent read command is received, it is not processed.

For example, the memory word register 50-2 of the memory 48 is read, so that the read address ring counter 36 reads the memory word register 50-2.
Assume that you are pointing to 2. At this time, the memory word registers 50-2 to 50-N are the same as 50-1.
New data can be written. Memory word
When register 50-1 is written, memory 48 is full. In addition, the read address ring counter 36 and the write dress ring counter point to the memory word register 50-2 to detect that the memory 48 is full when the last memory operation was a write operation. it can.

Conversely, the entire memory 48 has been written,
Thus, if memory word register 50-N has been written, write address ring counter 32 points to memory word register 50-1. In this situation, the memory word registers 50-1 through 50-N
Can be read after this, and the memory 48 is emptied.
Read and write address ring counters 32, 36
Point to the same memory word register 50-1, and when the last memory operation is a read operation, a memory empty condition can be detected.

[0012]

In the above circuit device,
The addressing is performed by the read address ring counter 32 and the write address ring counter 36. By managing the description of the last memory read and write operations, memory full and memory empty are identified. I have. However, in such an identification method using a counter, it takes too much time to determine whether the memory is full or empty, resulting in a considerably slow FIFO circuit in terms of cycle time.

An object of the present invention is to solve such a problem and to provide a high-speed FIFO circuit capable of quickly discriminating whether a memory is full or empty.

[0014]

According to the present invention, shift registers are provided on the write side and the read side of a memory, respectively.
A write clock and a read clock are input to each shift register means, an address generated by each shift register means is input to a word line and a comparison means of the memory, and the number of turns of the shift register generated by each shift register means Is input to the comparing means, and the comparing means outputs full address information indicating that the memory is full according to the address and the signal indicating the number of revolutions from each shift register means. Generating empty flag information indicating that there is, stopping the write clock when the full flag information is generated, and stopping the read clock when the empty flag information is generated. I do.

The comparing means generates the empty flag information when an address generated by each shift register means matches and a signal indicating the number of turns from each shift register means matches. If the addresses generated by the shift register means match and the signals indicating the number of turns from each shift register means are different, the full flag information is generated.

Further, the shift register means shifts the "H" level every time one clock is input to turn on the word line, and the number of turns of the "H" level of the shift register. And a flip-flop which outputs the data in an odd-numbered round and an even-numbered round.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a preferred embodiment of a high-speed FIFO circuit according to the present invention will be described with reference to FIG. In FIG. 1, a write-side shift register circuit 11 and a read-side shift register circuit 12 are provided for a memory 10. Write-side shift register circuit 1
1. The read-side shift register circuit 12 receives the write clock WCLK and the read clock RCLK, respectively.
The write address WADR and the read address RADR are input to the word line of the memory 10 and are input to the comparison unit 13. Data DI is written to the memory 10 based on the write address WADR, and data DO is read based on the read address RADR. The write-side shift register circuit 11 and the read-side shift register circuit 12 also provide a signal WT / F indicating the number of turns of the built-in shift register.
F and RT / FF are input to the comparison unit 13.

The comparison unit 13 provides full flag information FFL indicating that the memory 10 is full according to the write address WADR, read address RADR and signals WT / FF and RT / FF indicating the number of turns from each shift register circuit.
G, generates empty flag information EFLG indicating that the memory 10 is empty. When the comparison unit 13 generates the full flag information FFLG, the write clock WCLK
When the empty flag information EFLG is generated, the read clock RCLK is stopped.

Strictly speaking, the comparing unit 13 outputs the empty flag information EFLG when the write address WADR and the read address RADR match and the number of turns indicated by the signals WT / FF and RT / FF indicating the number of turns match. And write address WADR and read address RAD
R and WT / FF, RT indicating the number of revolutions
If the number of turns indicated by / FF is different, full flag information FFLG is generated. Here, the number of turns is represented by “odd number turns” and “even number turns”, and the signal WT / F
The number of turns indicated by F and RT / FF are both "odd number turns"
Alternatively, it is assumed that the number of turns matches in the case of “even number turns”.

The comparison section 13 will be described with reference to FIG. The comparator 13 determines whether the write address WADR matches the read address RADR.
Ex-OR (Exclusive OR) circuit 13-2 having -1 and signals WT / FF and RT / FF indicating the number of revolutions as inputs.
An inverter circuit 13-3 receiving an output of the Ex-OR circuit 13-2 as an input, a NAND circuit 13-4 receiving an output of the inverter circuit 13-3 and an output of the comparator 13-1 as an input,
The NAND circuit 13-5 receives the output of the Ex-OR circuit 13-2 and the output of the comparator 13-1.

With such a circuit configuration, when the write address WADR matches the read address RADR and the number of turns indicated by the signals WT / FF and RT / FF matches, the empty flag information is output from the NAND circuit 13-4. EFLG is generated, the write address WADR matches the read address RADR, and the signal WT / F
F, when the number of turns indicated by the signal RT / FF does not match, the full flag information FFLG is output from the NAND circuit 13-5.
It will be understood that is generated.

Next, the write-side shift register circuit 11 will be described with reference to FIG. The write-side shift register circuit 11 here includes a 32-bit shift register 11-1 and a toggle flip-flop 11-2. The shift register 11-1 shifts the “H (high)” level every time one clock is input, and turns on the word line reaching the memory 10. Therefore, the time required to determine the address and turn on the word line is determined by the flip-flop 1 constituting the shift register 11-1.
You only need one delay. The toggle flip-flop 11-2 is a flip-flop whose state changes when the “H” level goes around the flip-flops FF / 0 to FF / 31, and how many times the “H” level of the shift register 11-1 goes around. In this case, a signal indicating whether or not the data is output is represented by "1" for an odd number of revolutions and "0" for an even number of revolutions. The above configuration and operation are exactly the same for the read-side shift register circuit 12.

In any case, the empty flag information E
The FLG or the full flag information FFLG is generated in an RS-flip-flop (not shown), and the RS-flip-flop receiving the empty flag information EFLG outputs a signal instructing stop of the read clock RCLK and receiving the full flag information FFLG. The RS flip-flop outputs a signal instructing stop of write clock WCLK.

The preferred embodiment of the present invention has been described above.
ASIC (Application) used around U
Specific Custom Product)
It is suitable for use as a buffer (operating at about 100 MHz) compatible with a high-speed bus, and has a memory capacity of 32 words ×
8 bits, 32 words x 16 bits, 32 words x 32
A bit SRAM can be considered.

[0025]

According to the present invention, a shift register is used for address generation, and by comparing the "H" level position of the shift register, full or empty memory can be recognized at high speed. As a result, the cycle time can be greatly reduced. The input clock may be asynchronous.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-speed FIFO circuit according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a comparison unit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of a write-side shift register circuit illustrated in FIG. 1;

FIG. 4 is a block diagram showing an example of the related art.

[Explanation of symbols]

 DI input data DO output data WADR write address RADR read address WCLK write clock RCLK read clock EFLG empty flag information FFLG full flag information

Claims (3)

(57) [Claims] 1. A shift register means is provided on each of a write side and a read side of a memory. A write clock and a read clock are input to each shift register means, and an address generated by each shift register means is transferred to a word line and a memory of the memory. A signal indicating the number of turns of the shift register generated by each shift register means is input to the comparing means, and the comparison means inputs the signal indicating the address and the number of turns from each shift register means. Full flag information indicating that the memory is full according to
It generates empty flag information indicating that the memory is empty, stops the write clock when the full flag information is generated, and stops the read clock when the empty flag information is generated. A high-speed FIFO circuit characterized by: 2. The comparing means generates the empty flag information when an address generated by each shift register means matches and a signal indicating the number of turns from each shift register means matches. 2. The full flag information is generated when an address generated by a shift register means matches and a signal indicating the number of turns from each shift register means is different.
A high-speed FIFO circuit as described. 3. The shift register means includes an n-bit shift register that shifts the "H" level every time one clock is input to turn on a word line, and how many times the "H" level of the shift register goes around. 3. A high-speed FIF according to claim 1, further comprising a toggle flip-flop which outputs whether the operation is odd or even.
O circuit.