JP3520570B2 - Memory access control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, and more particularly to a memory access control device having a speed buffering ring buffer. 2. Description of the Related Art In a conventional memory access control device, a FIFO memory is used as a buffer for speed buffering. However, the FIFO memory needs to shift data itself at the time of reading, and the capacity of the buffer becomes small. As the size increases, the amount of data shift also increases, so that there is a problem that it is unsuitable as a buffer for a memory having a large capacity such as a DRAM. In order to solve the above problems, a memory access control device using a ring buffer instead of the FIFO memory has been proposed. The ring buffer of the memory access control device controls writing / reading of a plurality of storage units by separate pointers, and usually uses a part of the main storage as the ring buffer area and includes a pointer. Everything is managed by software. A hardware configuration of such a ring buffer is disclosed in Japanese Patent Application Laid-Open No. 5-165603 (hereinafter referred to as prior art). Next, a memory access control device (hereinafter, referred to as a conventional device) to which the above-mentioned prior art is applied is shown in FIG.
This will be described with reference to FIGS. FIG. 4 is a block diagram showing a schematic configuration of a ring buffer of a conventional device, and FIG.
FIG. 2 is a block diagram showing a schematic configuration of the embodiment. In FIG. 4, reference numeral 3 designates B for instructing data writing from a storage control unit (not shown) to the buffer.
A write pointer (hereinafter referred to as WRP) for inputting a UFWR signal and indicating a current write position to a buffer;
Is a read pointer (hereinafter referred to as RDP) for inputting a BUFRD signal for instructing reading from the buffer and for indicating a current read position to the buffer, and the write position and the read position are output as a WRP value and an RDP value. You.
Reference numeral 5 denotes a storage element group including a plurality of storage elements for storing data d from a bus (not shown), and reference numeral 6 denotes a buffer for selecting output data from the plurality of data from the storage element group 5 based on an RDP value. This is a data selection unit, which is constituted by, for example, a multiplexer (MUX).
Reference numeral 7 denotes a data holding unit, for example, a D-FF, which latches output data from the buffer data selection unit 6 in response to a clock that recognizes the BUFRD signal from the storage control unit.
Reference numeral 10 denotes a hardware ring buffer constituted by the WRP 3, the RDP 4, the storage element group 5, and the buffer data selection unit 6. FIG. 5 shows a schematic configuration of a storage element group 5 composed of N + 1 storage elements. Since each storage element has the same configuration, only the storage element m is shown in FIG. Are specifically disclosed. In the figure, 5m is an m-th storage element of a plurality of storage elements, 11 is a storage element number storage unit storing storage element numbers (0 to N) for distinguishing each storage element, and the storage element number is Corresponds to address data. 12 is an input selector for comparing the storage element number with the value of the WRP3;
A data holding unit that is enabled by a WRLT signal (write latch signal) from the ND gate 14 and latches data d from the bus. Next, the operation of the conventional device will be described with reference to a time chart shown in FIG. First, when a write cycle start signal is input from the CPU (not shown) to the memory access control device via the bus, the BUFWR signal is sent from the storage control unit to the WRP3, and the BUFRD signal is sent to the RDP4 and the data holding unit 7, respectively. Is output.
First, the WRP3 stores the WRP value = 0 in the storage element group 5
The RDP 4 sets the RDP value = 0 to the buffer data selection unit 6
Output to The input selection unit 12 in the storage element 0
The value = 0 is compared with the storage element number 0. If the result matches, the WRLT signal is output from the AND gate 14 to the data holding unit 15, and the data holding unit 15 is enabled, and the data holding unit 15 is enabled in the cycle "A3". Data d0 from the bus is latched at the rise of the clock signal. Next, the WR
When P3 is incremented and the WRP value becomes 1, a match signal is output from the input selection unit 12 in the storage element 1, so that the data holding unit 15 of the storage element 1 is enabled, and the clock in the cycle "A4" The data d1 from the bus is latched at the rise of the signal. On the other hand, in the cycle “A4”, since the RDP value = 0, the buffer data selecting section 6 selects the output data line 0 of the storage element 0 and outputs the data d0 to the data holding section 7. I do. Further, the data holding unit 7 stores the BUF
It is enabled when the RD signal is at the H level, and latches the data d0 from the buffer data selection unit 6 at the rising edge of the clock signal in the cycle “A4” and outputs it to the memory. At this time, the data d1 is not output to the data holding unit 7, but is held in the data holding unit 15 of the storage element 1. As described above, in the conventional memory access device using the ring buffer, the first write data d0 from the bus is read to the memory with a delay of one clock from the data write to the ring buffer. become. RAS, CAS, WE, and the like in the figure are control signals for designating an address in a memory (DRAM) and storing data at the address, as is well known. Also, AS
Is an address strobe signal, and ACK is an acknowledge signal. As described above, in the memory access device, upon receiving a write cycle start signal from the CPU, data is temporarily written to the ring buffer and the first data is stored. DRAM in anticipation
Etc. are written to the memory. At this time, one clock is used to store data in the ring buffer, and one clock is used to retrieve data.
There is a problem in that it takes a clock and a dead cycle of one clock occurs before the first data d0 is written to the DRAM. In addition, the write cycle to the DRAM must be shifted by one clock later in comparison with the time when the ring buffer is mounted and the time when the ring buffer is not mounted, and the speed of the write cycle is deteriorated. Such a memory access control device improves the access speed from the bus, but has a problem that the access to the memory bus is always delayed. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems of the prior art, to realize a ring buffer for speed buffering of a main storage device by hardware, to improve a bus throughput, and to improve a memory access speed. It is an object of the present invention to provide a high-efficiency memory access control device in which the above is improved. [0014] In order to achieve the above object, the present invention provides a plurality of storage elements provided in a ring buffer, each of which is provided with an identifiable unique value, A write pointer instructing one of the plurality of storage elements to write, a read pointer instructing one of the plurality of storage elements to read, and a bus provided in the storage element from a bus. A first data holding unit that latches data, a first output selection unit that selects one of the data held by the first data holding unit or the data that has passed through, and a data output from the storage element group. Data 1
And a second output selecting section for selecting one of the two and outputting the selected data as memory data. According to the present invention, the first data holding unit latches data from the bus when the writing is instructed by the write pointer, and the first output selecting unit stores the write pointer and the storage. When the element-specific value and the read pointer match, the through data is selected, and in other cases, the data held by the first data holding unit is selected. When launching,
Writing and reading of data to and from the storage element can be performed within the same clock. In addition, it becomes possible to operate writing and reading independently. An embodiment of the memory access control device according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the memory access control device of the present invention. In FIG. 1, reference numeral 1 denotes a memory 9 (DRAM)
, And a storage control unit that generates control signals such as RAS, CAS, and WE at a timing required by the DRAM, and a row address (Row address)
And a column address (Column address).
The WRP3 is incremented by a clock signal input when the BUFWR signal is valid.
4 is incremented by the BUFRD signal. However, the WRP3 and the RDP4 are configured to start counting from the second clock signal and the BUFRD signal, respectively. Other symbols indicate the same or equivalent components as those in FIG. Next, the schematic configuration of the storage element group 5 will be described with reference to the block diagram of FIG. In FIG. 2, 1
Reference numeral 3 denotes an output selection unit for comparing the storage element number, the value of WRP3 and the value of RDP4, and reference numeral 16 denotes data stored in the data storage unit 15 or data from the bus 8 according to the comparison result of the output selection unit 13. And an output data selection unit for outputting the data. 1
Reference numeral 7 denotes a through data line for directly transferring data from the bus 8 to the output data selection unit 16 without passing through the data holding unit 15. Other symbols indicate the same or equivalent components as those in FIG. Next, the operation of the present embodiment will be described with reference to a time chart shown in FIG. First, when a start signal of a write cycle is input from the CPU via the bus 8 to the memory access control device, the storage control unit 1 transmits data to the BUFFW.
The R signal is output to WRP3, and the BUFRD signal is output to RDP4 and data holding unit 7, respectively. The WRP3 sets the WRP value = 0 to the storage element group 5, and the RDP4 sets the RDP value =
0 is output to the storage element group 5 and the buffer data selection unit 6, respectively. The input selection unit 12 in the storage element 0
The value = 0 is compared with the storage element number 0. If the result matches, the WRLT signal is output from the AND gate 14 to the data holding unit 15, and the data holding unit 15 is enabled, and the data holding unit 15 is enabled in the cycle "A3". Data d0 from bus 8 is latched at the rise of the clock signal. On the other hand, the output selector 13 in the storage element 0
Are: WRP value = 0, RDP value = 0, and storage element number 0
And if the results match, the output data selection unit 16 selects the through data line 17 and outputs the data d0 from the bus 8 to the buffer data selection unit 6. At this time,
Since the RDP value = 0, the buffer data selection unit 6 selects the output data line 0 of the storage element 0, and outputs the data d0 from the storage element 0. The data holding unit 7 is enabled when the BUFRD signal is at the H level, latches the data d0 from the buffer data selection unit 6 at the rise of the clock signal in the cycle “A3”, and outputs the data d0 to the memory 9. As described above, in this embodiment, the data d0 can be simultaneously written to the ring buffer 10 and output to the memory 9 at the timing of the rising edge of the clock signal in the cycle "A3". Next, when the WRP3 is incremented to a WRP value = 1, the input selector 1 in the storage element 1
2, a match signal is output, and the data holding unit 15 is enabled as in the case of the storage element 0, and the cycle "A"
The data d1 from the bus 8 is latched at the rise of the clock signal at the time of 4 ". At this time, since the BUFRD signal is at the L level, the data holding unit 7 is disabled.
No new data is latched. Next, when the WRP3 is incremented to a WRP value = 2, the input selection unit 1 in the storage element 2
2, the data holding unit 15 is enabled as in the case of the storage elements 0 and 1, and the data d2 from the bus 8 is latched at the rise of the clock signal in the cycle "A5". On the other hand, the RDP 4 is incremented so that the RDP value becomes 1, and the buffer data selecting section 6 selects the output data of the storage element 1. At this time, the storage element 1
Output selection unit 13 compares WRP value = 2, RDP value = 1, and storage element number 1. Since the results do not match, the output data selecting unit 16 selects the data holding unit 15 and outputs the data d1 held in the data holding unit 15 to the buffer data selecting unit 6. At this time, BUF
Since the RD signal is at the H level, the data holding unit 7
Is enabled, and the data d1 from the buffer data selection unit 6 is latched and output to the memory 9 at the rise of the clock signal in the cycle "A5". Thereafter, since the same operation as described above is performed, the description is omitted. As described above, according to this embodiment, the first data in the write cycle can be held in the data holding unit 15 and the data from the bus 8 can be output to the memory 9 as it is. For the second and subsequent data, the data from the bus 8 is stored in the data holding unit 15 in the storage element having the storage element number that matches the WRP value as the WRP value is incremented. Are sequentially written, and the data from the storage element selected by the buffer data selection unit 6 can be output to the memory 9 at the timing when the BUFRD signal becomes H level. As is apparent from the above description, according to the present invention, at the time of starting a write cycle, data can be written to and read from a storage element within the same clock. Therefore, a dead cycle does not occur, and it is possible to prevent an initial speed degradation at the time of starting a write cycle. In addition, writing and reading can be operated independently of each other. Therefore, the write and read operations can be performed simultaneously or in parallel, and the bus throughput by buffering can be improved without impairing the access time to the memory. Also, even if the number of storage elements in the buffer increases, the amount of increase in the circuit only increases linearly and does not become extremely complicated, so that the storage capacity of the ring buffer can be easily increased. Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a memory access control device of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of a storage element group according to one embodiment. FIG. 3 is a time chart for explaining the operation of one embodiment. FIG. 4 is a block diagram showing a schematic configuration of a ring buffer of a conventional device. FIG. 5 is a block diagram illustrating a schematic configuration of a storage element group of a conventional device. FIG. 6 is a time chart for explaining the operation of the conventional technique. [Description of Symbols] 1 ... storage control unit, 2 ... multiplexer, 3 ... write pointer, 4 ... read pointer, 5 ... storage element group, 6 ... buffer data selection unit, 7, 15 ... data holding unit, 8 ... bus, 9 memory, 10 ring buffer, 11 storage element number storage unit, 12 input selection unit, 13 output selection unit,
16 output data selection unit

Claims (1)

(57) A memory access control device comprising a ring buffer for speed buffering and controlling a memory in response to a request for access to the memory from a bus, wherein: A plurality of storage elements provided with an identifiable unique value provided; a write pointer for instructing one of the plurality of storage elements to write; and one of the plurality of storage elements A read pointer for instructing a read, a first data holding unit provided in the storage element, for latching data from a bus, and the data held by the first data holding unit or the through data. A first output selection unit for selecting one of the data, and selecting one of the data output from the storage element group,
A second output selection unit for outputting as memory data, wherein the first data holding unit latches data from a bus when writing is instructed by the write pointer, and the first output selection unit Selects the passed data when the write pointer, the storage element-specific value, and the read pointer match, and otherwise selects the data held by the first data holding unit. A memory access control device characterized by having such a configuration.