JP2550359B2 - Method and apparatus for simultaneously operating address increment and memory write - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates generally to first-in-first-out (FIFO) memory for asynchronous transmission of digital signals, particularly as contained within a FIFO memory. A method and apparatus for addressing memory registers.

It is well known to use memory as an intermediate buffer between system components in order to store data written by a transfer device at one rate and read from it at another rate by a destination device. It is a technique. First-in first-out (FI
The random access memory for the buffer which operates by FO) system has been developed. In particular, pending US Patent Application No. 746,920, filed June 20, 1985, discloses a FIFO memory device that can be written and read in a very short time.
The FIFO memory comprises a plurality of memory word locations having a common data input bus for writing data directly to the memory location and a common data output bus from which data can be read directly. A write address ring counter sequentially addresses each memory word location in response to an input write command. Similarly, the read address ring counter operates to sequentially read memory word locations in response to an input read command.

This FIFO memory write command generates a write clock pulse consisting of a first negative going transition and a second positive going transition. On a negative transition, the address is incremented to the next location. On the subsequent positive transition, the address location where the pointer was incremented is written to the memory register. As will be discussed in more detail below, guard bands or buffer times are typically inserted low in the write cycle to avoid writing to the wrong address.

The pending U.S. Patent Application No. 746,920 writes at the high portion of the inverted write clock pulse and increments the address pointer at the low portion of the next inverted pulse.
Also, a guard band is placed in the lower part. The high and low portions are generally long enough to allow complete completion of the above operations. The spacing between the leading edges of the write commands is equal to the combined length of both the high and low portions.

The read cycle of this FIFO is much shorter than the write cycle. Maximum frequency Fmax for data transmission through FIFO
Is the reciprocal of the maximum allowable read and write cycle length because all FIFOs can read new data only as fast as the previous data can be read. Therefore, the above-mentioned US patent application
Although FIFO memory significantly improves throughput time, throughput time can be further reduced if both the minimum acceptable read and write cycles are approximated.

SUMMARY OF THE INVENTION The present invention discloses and claims a method and apparatus for sequentially addressing multiple memory registers in a short amount of time. The write clock pulse is generated in response to the write command and has first and second transitions. Upon receiving the first transition of the write clock pulse, the write address generator increments from its first location to the next location. Further, at the first transition, the stored first address signal becomes the first
It is transferred to the memory register corresponding to the location.
Upon receiving the second transition of the write clock pulse, the next address signal from the next location of the write address generator is stored.

In the preferred embodiment, the address generator has an output connected to the inputs of a plurality of transparent latches, one latch for each memory register. Each latch also has an output connected to one input of a respective NOR gate. The output of each NOR gate is connected to its respective memory register. The write clock line is connected to each transparent latch and the input of each NOR gate, and further connected to each of a plurality of ring counters or address generation stages. Each ring counter stage corresponds to an address location.

The first address signal from the first stage is stored in the first latch in response to the positive transition clock pulse transition. When the next negative transition is received, the address location pointed to by the pointer is incremented from the first stage to the second stage,
The address signal is available at the input of the corresponding second transparent latch. At the same time, the negative transition causes the first address signal stored in the first latch to be written to the first address via the respective NOR gate. Then, the same process is repeated for the subsequent stages.

The main advantage of the invention is that the guard band in the high part of the high pulse of the clock pulse is no longer needed. Also, since both the increment of the address generator and the memory writing are performed in the low part of the write clock signal, the high part of the write clock signal is not required for 4 or 5 ns or more, and the address is generated between the increments of the stages. The vessel is recoverable to prevent unwanted race conditions and stabilize the circuit. Thus, significant time savings are realized, the maximum allowable write cycle frequency approaches the maximum allowable read cycle frequency, and the FIFO memory has a correspondingly faster data throughput.

Other advantages and features of the invention will be apparent from the following description of exemplary embodiments with reference to the accompanying drawings.

Although the present invention has a wide range of applications in digital communication, an example environment in which the present invention can be advantageously implemented is shown in FIG.
A FIFO memory buffer, schematically represented by reference numeral 10,
A high speed data processor 12 and a low speed cathode ray tube (CRT) terminal device 1 connected via a FIFO memory buffer 10 during communication.
It is shown as being located between four. Data communication occurs in the direction from the data processor 12 to the CRT terminal device 14, and in the illustrated example, the data processor 12 operates at a much higher speed than the CRT terminal device 14 can read.
It can be written in the FO memory buffer 10. The data processor can achieve a transfer rate of about 9600 bits per second, but CR
A general peripheral device such as the T terminal device 14 can only transmit data at 1200 bits per second.

Therefore, the FIFO memory buffer 10 provides an intermediate data storage means capable of writing data at a first speed and reading data at a different second speed. However, it should be understood that the FIFO memory buffer 10 of the present invention can be used with the same effect even when the data writing speed is lower than the data reading speed. If the data transfer to the FIFO memory buffer 10, i.e. the data write operation is faster than the data read operation, the main problem is the detection of a completely filled memory,
The point is to notify the data processor 12 of the detection so that the transfer of data can be interrupted. On the other hand, when the speed of the data read operation exceeds the speed of the data write operation, the main problem is the detection of the empty FIFO memory buffer 10. In this case, the detection of the above-mentioned state should be taken with sufficient time so that the subsequent read command from the CRT terminal device 14 does not cause a meaningless read operation of the emptied FIFO memory buffer.
The CRT terminal 14 must be notified.

However, in actual digital data communication, a short burst of high-speed data write operation fills the buffer memory, while a long burst of low-speed data read operation empties the memory buffer, resulting in both empty and full memory buffers. May occur. Thus, the FIFO memory buffer 10 may encounter both empty and full states, regardless of whether the originating or destination device is a fast or slow device, respectively.

Referring again to the exemplary system of FIG. 1, since the data flow is from the data processor 12 to the CRT terminal 14, the data input bus 16 is from the data processor 12.
Provides a transmission medium to the FIFO memory buffer 10. There is a write command line 18 associated with the data input bus 16 and each word of data transmitted on the data input bus 16 is associated with a write command on line 18. FIFO memory buffer
Full flag line from 10 to data processor 12
20 is provided to signal the data processor 12 that the memory buffer is full. Details of the full flag will be dealt with in detail later.

To complete the entire transmission line from the data processor 12 to the CRT terminal device 14, a data output bus 22 from the FIFO memory buffer 10 to the CRT terminal device 14 is provided.
Digital data is transferred from the FIFO memory buffer 10 to the CRT terminal device 14 by a read command issued from the CRT terminal device 14 to the FIFO memory buffer 10 via the read command line 24. That is, data is read from the FIFO memory buffer 10 and output on the data output bus 22 at the rate at which the read command appears on the read command line 24.

When the FIFO memory buffer 10 is empty, the empty flag line 26
A signal is sent to the CRT terminal device 14 via the. Reset line 28 from data processor 12 and CRT terminal 14 to FIF
To the O memory buffer 10, the memory buffer is initialized to a desired initial state.

Referring to FIG. 2 of the drawings, the features of the basic structure of a FIFO memory buffer 10 according to the present invention are shown.

The write / read (W / R) controller 30 is used by the data processor 1
It receives write and read commands from the CRT terminal device 2 and the CRT terminal device 14, respectively, and controls write and read of the memory 48. W / R
The controller 30 sends the corresponding write / read signal to the write line 34.
Multi-stage write address generator or ring counter via
32 and then via read line 38 to a multi-stage read address generator or ring counter 36. As discussed in detail below, W / R counter 30 maintains a determination as to whether the last memory operation command processed was a write or read command.

A plurality of logic gate comparators 40 are connected to the write address ring counter 32 and the read address ring counter 36 by a plurality of conductors 42 and 44, respectively. The comparator 40 is also connected to the W / R controller 30 via line 46,
A signal is generated when the write and read address ring counters 32, 36 point to the same address. As detailed later,
With this information, the W / R controller 30 can determine when the memory 48 is full or empty.

Memory 48 has a memory word location or register 50 ₁ to 50 _N to store the word 1~N respectively. Each memory word register 50 _i is uniquely connected to each stage of the write address ring counter 32, and performs a memory write operation to those memory word registers. Further, each memory word register is also connected to each corresponding stage of the read address ring counter 36 to perform a memory read operation. Hereinafter, the memory word location addressed during a write or read operation is referred to as being pointed to by one of the ring counter or address generator 32 or 36. The read address ring counter 36 is the write address ring counter.
Memory 48 is full when it points to the same memory word register 50 _i as 32 and the last memory operation is a write operation. Similarly, both write and read address ring counter 3
When 2,36 point to the same memory word register 50 _i and the last command received is a read command, the receipt of another read command is not processed because memory 48 is empty.

For example, the memory word register 50 of the memory 48 in FIG.
Assume that ₂ is read, and thus read address counter 36 points to register 50 ₂ . New data can now be written to the memory word registers 50 ₂ to 50 _{N and} further to 50 ₁ . If written to the memory word register 50 _1, the memory 48 is full. Further, the read address ring counter 36 and the write address ring counter 32 points to register 50 _2, the last memory operation is a write operation.

Conversely, the memory 48 overall is written, thus if written memory registers 50 _N is, write address ring counter 32 points to register 50 _1. In this state,
Registers 50 ₁ to 50 _N can be read sequentially until memory 48 is empty. Memory is empty refers to read and write both addresses ring counter 32, 26 are the same memory register 50 _1,
And it will be clear that it can be detected when the last memory operation is a read operation.

According to the method, it is not necessary to keep a particular memory address in the table, what is needed (in any case) is information about whether the read and write addresses are equal and processed. It should be appreciated that the last memory command is only information about whether it is a read or write operation.

Referring again to FIG. 2, the memory word register 50 ₁
Has a data input 56 commonly connected to the data input bus 16. Each of the remaining memory word registers 50 _2-N also includes a similar connection to data input bus 16. Similarly, each memory word register 501 _-N has a data output 58 commonly connected to the data output bus 22. The data input and output buses 16 and 22 each consist of 5 bit lines corresponding to the number of data bits of the memory word (FIG. 4). In the exemplary FIFO memory buffer 10 described herein, there are N memory words that store N data words, each exemplary word being 5 bits long. Of course, the data words of the FIFO memory buffer 10 can easily be extended to accommodate other popular bit lengths such as 8, 16 or 32 bits.

As described above, the write address ring counter 32 includes a large number of stages 32 _i , and each stage has a write clock (WRITE CLOCK).
It is connected to line 34 (Fig. 4). Each stage 32 _i also corresponds to a memory word register 50 _i and operates to direct a write signal to the respective memory word register. As will be described in greater detail below, memory 48 is read or written starting at word 1 and proceeding to word N before repeating the same sequence again.

Read address ring counter 36 includes similar stages for similarly sequentially reading N memory word registers 50. Each stage of the read address ring counter 36 is connected to the read signal line 38.

Using this method of maintaining a decision about the last read and write operation and comparing whether both read and write memory addresses are equal, a very accurate determination of the full or empty state of memory 48 can be made.

Unlike conventional schemes, the cyclic operation of the FIFO memory buffer 10 depends only on the leading edges of the read and write command inputs at 18 and 24 and not the timing of their trailing edges. As described above, events that occur outside the FIFO memory buffer 10, such as data changes on the data input bus 16, or the memory 48
The above fact is extremely advantageous in that the nearly simultaneous read or write operations that occur when is empty or full do not result in undesired operation of the FIFO memory buffer 10. To this end, the W / R controller 30 includes circuitry that generates a complete internal read and write pulse based on the leading edge of a read or write command. FIG. 3 shows the write signal generator 60 of the W / R control device 30 in a simplified form.

Against the background described above, please refer to FIGS. 3, 4 and 5 which show the operation of the FIFO memory buffer 10 in more detail.

In FIG. 3, the input of the write signal generator 60 is shown with a waveform representing the leading edge of the write command, and the resulting write clock pulse labeled "Write Clock". A buffer gate 62 isolates the write command line 18 from the rest of the FIFO memory buffer circuit. Monostable multivibrator 64 receives the same write command signal as on line 18 through its gate delay but at its input. The monostable multivibrator 64 is of a type that produces an output pulse in response to a rising transition. Resistor and / or capacitive components (not shown) connected to the interior or exterior of monostable multivibrator 64 are selected to produce output pulses of the desired width. In the preferred embodiment of the invention, the monostable multivibrator 64 is 10-15 ns.
Generate an output pulse of width.

Also of particular importance is a write enable latch that responds to the leading edge of the write command after inversion by inverter 98 and inhibits the passage of write clock pulses through NAND gate 68.
66. It will be appreciated that this prohibition will only occur if both read and write address ring counters 36, 32 point to the same memory word and the previous operation was a write operation. A final W / R operation flip-flop 70 is provided to maintain a determination of whether the last memory operation was a read or write operation of memory 48. The final W / R operational flip-flop 70 is connected to the "D" input of the write enable latch 66 and gives an indication as to whether the monostable pulse should pass through the NAND gate 68.

The read signal generator 80 of FIG. 4 also responds to the leading edge transitions of the read command and reads the read line when memory 48 is not empty.
Generate a read pulse on 38. More specifically, monostable multivibrator 84 is connected to one input of NAND gate 86. Inverter 88 inverts the read command signal and connects it to read enable latch 90. The output of read enable latch 90 is connected to one input of NAND gate 86.

FIG. 4 shows a detailed electrical wiring diagram of the FIFO memory buffer 10 according to the present invention. Roughly speaking, memory
Unless 48 is full or empty, W / R controller 30 will generate a write clock pulse signal on write line 34 and a read clock pulse signal on read signal line 38 in response to the corresponding input command. To do. The read address ring counter 36 and the write address ring counter 32 each comprise a shift register having a plurality of 1-bit stages 36 _1-N and 32 _1-N . Both ring counters 32 and 36 sequentially shift one logic high bit through each location or stage therein to point to a particular memory word to be read or written.

Comparator section 40 includes a plurality of two-input NAND gates that determine the empty and full states of memory 48. NAND gate 40 _b of the comparator 40, the address output of the read address ring counter 36 is compared with the address output of the write address ring counter 32, used to make a determination of whether the memory 48 is empty or full W / R control device 30 (on line 46)
To be supplied together. Specifically, NAND gate 40 _b1 compares the output of read address ring counter stage 36 _{1 with} the output of write address ring counter stage 32 ₁ . NAND gate 40
_b2 compares the outputs of both stages 36 ₂ and 32 ₂ , and so on. That is, NAN
D gate 40 _b is compared with the address ring counter stage 36 and the next write address ring counter stage 32 reading.

Memory 48 includes input data latches, such as latch 74, where input data from data input 16 is latched in response to trailing edge transitions of a write command signal on line 75. The data output bus 22 comprises the outputs of a number of tri-state drivers 76 which provide the power to drive the data output bus 22 destined for the destination device. 3-state driver 76
The high impedance state control device 78 for is also an auxiliary line directed to the destination device.

Next, the FIFO memory buffer shown in FIG. 4 will be described with reference to a general operation cycle.

A negative pulse on reset input line 28 is applied to initialize the various circuits within FIFO memory buffer 10 to the desired state. Specifically, the signal on reset line 28 resets the last R / W operational flip-flop 70, the output of which is at the theoretical high level. The reset line 28 is also connected to the reset input "R" of the read and write address ring counter stages 36 _2-N and 32 _2-N and the set input "S" of stages 36 ₁ and 32 ₁ . Therefore, each address output of ring counter stages 36 _2-N and 32 _2-N is reset to a logic low, while ring counter stages 36 ₁ and 32 ₁ are set to an output logic high level. The reset signal is also connected to the AND gate 41 to initialize the flip-flop 136.

Since the reset signal is typically issued at or after powering up the FIFO memory buffer 10, reliable data should not be considered present in memory 48. Therefore, at least the reliable data is the first memory register.
Until the write operation to be present in 50 ₁ is executed, reading the first memory is to be prohibited. In fact the first read command is issued to the empty FIFO memory buffer 10,
It will be appreciated that even if the read signal generator 80 produces a read signal at the input of the NAND gate 86, the resulting read clock pulse does not appear on the read line 38.

Reset line 28 is the last R / W active flip-flop 7
Since the output of 0 causes a logic high to appear, if the output of inverter 22 were high for a short time, both inputs of AND gate 94 would be a logic high, thus producing a logic high at its output. The read enable latch 90 is a D-type transparent latch such that the complement of the logic level appearing on the D input is transferred to the output as long as the enable input E is a logic high. When enable input E is low, its output is latched at the logic level of the data set on the low transition. The Texas Instruments SN74LS364 transparent latch is an example of a latch that performs the above operation.

Thus, on the positive going leading transition of the input read command, the corresponding low going transition of the output of inverter 88 latches the complement of the logic high at the D input of transparent latch 90 as the logic low of the output. And the output logic low is connected to the input of NAND gate 86.

That is, read enable latch 90 pulls one input of NAND gate 86 low, which inhibits the transfer of the read signal generated by monostable multivibrator 84 in response to the first read command.

However, since the Q output of the final R / W operation flip-flop 70 is initially set to the logic low level, AND
The output of gate 96 provides a logic low level to write enable latch 66. Write command inverter 98 inverts the rising edge of the write command to a negative going edge and applies it to the E input of write enable latch 66. This provides a logic low on the D input of latch 66 as a logic high on the output to input 100 of NAND gate 68. The third input of NAND gate 68 is also high as a result of the output of buffer 62 being a logic high. Therefore, the write pulse generated from the monostable multivibrator can pass through the NAND gate 68.

The write monostable routine 64, shown in block form in FIG. 3, actually comprises a buffer gate 102, an inverter 104 and a timing capacitor 106. It will also be apparent that the positive transition pulse of the write command is provided from buffer gate 62 to one input of NAND gate 68. The post-buffer write command is also applied to the input of another buffer 102. The timing capacitor 106 keeps the input of the inverter 104 following the input of the buffer gate 102, delaying the rising edge transition until the input threshold of the inverter 104 is reached, when the threshold is reached. Goes to a logic low level, returning the output of NAND gate 68 to a logic high. Thus, with the above circuit arrangement, the rising edge transition of the write command causes a write clock pulse on write clock line 34.

Referring briefly to FIG. 5, a write clock pulse is generated on line 34. Waveforms within the W / R controller 30 are shown. It is clear from these waveforms that the output of inverter 98 goes low on line 75 and the output of write enable latch 65 latches to a logic high as a result of the positive transition on the leading edge of the write command. Ah At the same time, the output of buffer gate 62 goes to a logic high level and two logic highs appear at the two inputs of NAND gate 68. Inverter 104
Since the timing capacitor 106 on the input side of the delay delays the output of that inverter to a logic high, the NAND gate 68
The third input of also goes high, causing a low transition of the WRITE CLK. When the timing capacitor 106 is charged to the voltage 108 corresponding to the input threshold value of the inverter 104,
The output of the inverter 104 becomes low as shown in the waveform, and the NAN
The output of D-gate 68 is driven high to complete the write clock pulse. Waveform dimension 109 in FIG. 5 represents the amount of time required for timing capacitor 106 to charge sufficiently to provide a logic high to the input of inverter 104 and bring its output to a logic low level. The larger the value of the timing capacitor 106, the larger the width of the write clock pulse on the write line 34.

From the above, it will be apparent that the W / R controller 30 produces the write clock pulse WRITE CLK in response to the leading edge of the write command. Read signal generator 80 of W / R controller 30 is similarly configured to generate a read clock pulse READ CLK on read line 38 in response to a read command.

Also in response to the write command, the output of inverter 98 goes to a low transition on line 75, at which time the data input bus
Latch the digital data present on 16 into their respective transparent data input latches 74. That is, the buffer inverter 110 receives 5 data bits of each data word transmitted via the data input bus 16 and converts each voltage on the transmission line into a digital signal compatible with the circuit voltage of the FIFO memory buffer 10. . The output of the buffer inverter 110 provides each data bit with the output of the inverter 112,
The complement is provided to each input data latch 74. This circuit configuration causes the digital data currently present on the data input bus 16 to be latched in the input data latch 74 at the beginning of the write cycle. This is advantageous in that any changes in digital data on the data input bus 16 that occur immediately before or after the write command leading edge transition are ignored.

The Q output of each stage 32 _i becomes an input to block 150 which operates to address a memory register 50 _i which is conceptually pointed to by a pointer. Read signal line 120 is blocked
Through 150, which functions as a reading address input of the register 50 ₁ to 50 _N. In addition, block 150 outputs
It has a plurality of write signal lines 116 that each transfer a write address signal to a respective register 50 _i . The write clock line 34 is an output from the NAND gate 68, and is connected to each of several stages of the block 150 as described later. Each stage of block 150 also connects its respective ring counter stage to the Q output and write signal line 116. Further details of block 150 may be found in pending U.S. Patent Application No. 746,920.
Unlike the structure shown in FIG. 6, detailed description will be given below with reference to FIGS. 6a, 6b, 7a and 7b.

Referring first to FIG. 6a, said pending US patent application No. 74
A write control circuit based on the structure shown in 6,920 will be described. Inverted write clock pulse on line 152 However, each register stage 32 _i of the write address ring counter 32
Enter crolock at the same time.

Is the inversion of the WR CLK pulse appearing on line 34 (Fig. 4), where WR CLK is driven by an inverter (not shown) Is converted to. Each write address ring counter stage 32 _{1 to} 3
The 2 _N Q output is connected to the adjacent higher order D input. However, the Q output of stage 32 _N is connected back to the D output of the first stage 32 ₁ . Therefore, at the low transition of WR-CLK, stage 32 ₁
The logic high of the output of Q ₁ (obtained on reset at Q ₁ ) is shifted to the output Q ₂ of stage 32 ₂ .

As with, the Q output appears as an input to NAND gate 114.

Taking Q1 as an example, And Q1 are both high, NAND gate 114 produces a low output on line QD1, which is input to inverter 153. The inverter 153 is QD1 input, inverts the high signal on the write signal line WS _1. The positive transition of the positive pulse on line WS ₁ initiates the writing of the 5 data bits latched in input data latch 74 to the corresponding cell or bit position in memory word 50 ₁ .

Referring to FIG. 7a, a timing diagram corresponding to FIG. 6a is shown. Step 32 _i As it senses the negative going transition of the pulse, the generator or ring counter increments from stage 32 ₁ to stage 32 ₂ at time 158. As a result, the Q1 output goes low and the Q2 output goes high. The transitions of Q1 and Q2 are not instantaneous, but curves 160 and 1 respectively.
Shows 62. During a certain period T ₁ , Q2 rises above a certain threshold at which NAND gate 114 ₁ senses high power, but Q1 does not decay below the above threshold for gate 114 ₁ . Therefore, Q1 and Q2 together provide a high to each NAND gate during period T ₁ .

Here, Let the period between pulses be T ₂ . T ₂ will change depending on when the leading edge of the next write command is received on line 18 (FIG. 4). If T ₂ is less than T ₁ , then each NAND gate 11
4 Therefore, there is a conflict between the memory registers 50 ₁ and 50 ₂ as to which memory register should be addressed.
Therefore T ₂ must always be greater than the sum of T ₁ and the guard band. It has been found that T ₂ should not be less than about 10 ns in the actual structure of the FIFO memory structure based on the state of the art. The length of the write signal pulse WS ₁ shown by T ₃ in FIG. 7a is Is controlled by the positive pulse of, and ultimately by the value of the timing capacitor 106 in the monostable multivibrator 64. About because 20ns required to write from the latch 74 to one of the memory registers 50 _i, T ₃ should not be less than the duration. The sum of T ₂ and T ₃ is line 18 (4th
Figure) determines the minimum interval between the positive transitions of adjacent write command pulses received above. In a FIFO memory that uses the latest semiconductor device technology, the above intervals are approximately 30
Limited to ns. Therefore, the maximum write transmission frequency 1 / (T ₂
+ T ₃ ), or about 33 MHz. The operating frequency Fmax of the FIFO memory is the smaller of the maximum read frequency and the maximum write frequency. Since the write frequency is about half the read frequency in this structure, the maximum write frequency determines Fmax.

6b and 7b, there is shown a write clock circuit and timing diagram according to the present invention. For ring counter stages 32 _{1 to} 32 _N , each stage 32 _i It is connected as in FIG. 6a, except that it is connected to the WR CLK line 34 instead of line 152. However,
The Q output of each stage 32 _i is connected to the D input of a transparent latch 154 _i , respectively. Each transparent latch 154 _i has a WR CLK line 34
And an output connected to one input of each NOR gate 156 _i . Each NOR gate 156 _i
WR CLK is added to the other input. The output of each NOR gate 156 _i becomes a write signal line 116 connected to a respective memory register 50 _i .

In operation, a negative transition transition 164 (FIG. 7b) causes the ring counter to move the write bit from stage 32 ₁ to 32 ₂ and increment the pointer from location 1 to 2. Q1
Is low, Q2 is high, and these values are transparent latches 154 ₁ ,
154 ₂ given to each input. Since positive-going transition of the last time is made to latch the high bit of Q1 in the transparent latch 154 _1, this appears at its inverting output line ▲ ▼. NOR
When the negative transition transition 164 is received by gate 156 ₁ , the positive write address bit is passed to memory register 50 ₁ . That is, the negative transition transition 164 increments the address generator from the first location to the next location while simultaneously addressing the first memory register.

The next positive transition of WR CLK is shown at 166. This is Q
1 (now 0) a transparent latch 154 in _1, Q2 (now 1) are respectively the clock input of the transparent latch 154 in _2. In response, ▲ ▼ becomes high and ▲ ▼ becomes low. When a negative transition transition is received by the NOR gate 156 _2, "1"
Address bits are passed to the memory register 50 _2. Then, finally at the same time writing the ring counter is incremented to the stage 32 _1, to a high address bits from stages 32 _N and latch 154 _N is passed to the memory registers 50 _N, the above cycle is repeated.

The present invention saves memory write time in two ways. First, both the address generator increment and the memory write operations are performed on the low side of WR CLK. Therefore, T ₂ and T ₃ occur at the same time, and only the latter need be considered to determine Fmax. The latter, of course, is T ₃ , which is about 20 ns. To a 2, T ₃ is a fairly long period, competition between NOR gate can not occur. For example, referring to FIG. 7b, ▲ ▼ and ▲ ▼ are in their respective new states much longer before the negative transition transition 168 of WR CLK begins. Therefore, no guard band is needed. The positive pulse on WR CLK need only be long enough to prevent stage 32 _i from recovering from a previous increment and causing undesired progress to occur elsewhere in the circuit. Such pulses can be as small as about 4-5 ns. In the preferred embodiment, the write frequency or Fmax is possible up to 1 / (20 + 5) ns = 40 MHz.
Therefore, the speed of the entire FIFO memory is greatly improved.

Returning to FIG. 4, each bit storage area 118 of memory register 50 _i has a logic high level at its respective read and write inputs that causes a corresponding read or write of all bits in memory word register 50 _i . Such a cross-coupled latch. Memory word register 50 ₁ to 50 _N each bit cell
The cross-coupled latch forming 118 is of conventional design.

As mentioned above, the signal applied to the reset line 28 is
By setting the Q outputs of stages 36 ₁ and 32 ₁ to a logic high state and resetting the other stages so that their output states are a logic low, the read and write address ring counters 36, 32 are reset. initialize. The bit cell of each memory word register 50 is configured to perform a read operation when the memory read signal line 120 is in a logic high state.
The write operation is performed while there is a high state on line 116.

In the present invention, after being reset by the reset 28,
Memory 48 can be considered empty or having unreliable data. Subsequent reads that do not intervene a write operation should be prohibited because reading empty memory will result in invalid data. The NAND gate 40 _b1 of the comparator has an input connected to the output of the read and write address ring counter stages 36 ₁ , 32 ₁ , so that after initialization the output of NAND gate 40 _b1 is a logic low. This logic low is directed to the input of inverter 122, which in turn drives a logic high to the inputs of both AND gates 94, 96 of the last R / W operation flip-flop 70. As mentioned above, this prevents the first read command from being processed.

Last R / W flip-flop 70 during reset 28
Since the Q output of is set to a logic low, this logic low is routed through the AND gate 96 and the write enable latch 6
Appears on D input of 6. A negative going transition on the E input of latch 66 causes a low logic on the D input to appear as a logic high on the output, allowing the first write command to be processed through write signal generator 60. The write clock pulse thus generated appears on line 34, setting the Q output of the final R / W operation flip-flop 70 to a logic high and clocking the write address generator 32. The Q output of each write address ring counter stage is connected to the D input of the adjacent higher order stage so that the logic high initially set in the write address ring counter 32 ₁ will result in consecutive WR on line 34.
Shift through each register stage position in response to a negative going transition of the CLK pulse. This causes the write command to be written to memory word location 50 ₁ at the same time that the logical high originally at the Q1 output of write address ring counter stage 32 ₁ is shifted to the Q2 output of counter stage 32 _2. Is done.

Subsequent write and read operations are performed by the NAND gate of each comparator.
40 _b1 to 40 _bN have a logic low at one of their inputs, which is possible in that order by providing a logic high level to inverter 122. That is, the output of the inverter 122 is line 4
A logic low on 6 is applied to both AND gates 94, 96, and a logic low is applied to the D inputs of the write and read enable latches 66, 90. As a result, the outputs of both latches 66, 90 are at a logic high, allowing further write and read operations.

In fact, as long as the write address ring counter 32 precedes the read address ring counter 36, subsequent write and read operations can occur and can be performed simultaneously. Unless the same memory word register is pointed to by both read and write address ring counters 36, 32, the write circuit is totally independent of the read circuit, so that simultaneous read and write commands can be issued to the FIFO memory buffer. It can be processed at 10.
However, when such a state exists, the last R / W operation flip-flop 70 has priority over both AND gates 94 and 96, and the independence of read and write operations is changed. This is because when the same memory word register is addressed by the read and write address generators 36, 32, the inverter 12
2 output goes high, the last R / W operation flip-flop 70
Of either the read signal generator 80 or the write signal generator 60, respectively.
It will be clear from indicating what is enabled via 0,66.

Therefore, the last R / W operation flip-flop 7 to determine whether the read or write command was the last operation.
Comparator 40 that detects when 0 is both read and write address ring counters 36, 32 pointing to the same memory word.
It will be appreciated that in cooperation with, it ensures that memory words are not read when the memory is empty and not written when the memory is full. Also, the last R / W operation flip-flop 70
In conjunction with this, read and write signal generators 80, 60 are provided which provide a secure lockout of the read and write commands when the processing of the commands results in an empty memory read or a full memory write.

The empty or full states of memory 48 detected by comparator section 40 are output 26 (empty; EMPTY) and 20 (full; F, respectively).
ULL) to other equipment. Empty of memory 48 /
The circuit for generating the full state signal is connected as follows.

NAND gate 40 _a1 has read address ring counter stage 36
Compare ₁ to the higher order write address ring counter stage 32 ₁ . NAND gate 40 _a2 compares read counter stage 36 ₂ with higher order write counter stage 32 _3, and so on. Thus, the address ring counter stage 36 NAND gate 40 _a is read respectively compared to the high-order write address ring counter stage 32.

NAND gate 40 _c1 is the write address ring counter stage 32 ₁
Outputs, compares higher the reading address ring counter stage 36 _2. NAND gate 40 _c2 drives write stage 32 ₂ to higher read stage 3
6 Compare with ₃ mag. That, NAND gate 40 _c is compared with the read address ring counter stage 36 of the high-order write address ring counter stage 32, respectively.

The output of each NAND gate 40 _a is one input of AND gate 41 is connected to the common to the input. The other input of the AND gate 41 is connected to the reset (RE SET) signal line. The output of the AND gate 41 is connected to the set input of the flip-flop 136. Similarly, the output of each NAND gate 40 _c is connected to the common to the reset input of the flip-flop 136.

The output of the inverter 122 is connected to one input of the NAND gates 138 and 140. The Q and output of the flip-flop 136 are connected to the other inputs of the NAND gates 138 and 140, respectively. Further, the output 26 of NAND gate 138 produces a signal indicating the empty state of memory 48 and the output 20 of NAND gate 140 produces a signal indicating the full state.

In operation, NAND gates 40 _a, 40 _b of the comparator 40 is detects respective states of Ho Isuzu empty or Ho Isuzu full memory, the flip-flop 136 is reset or set accordingly. Specifically, when only one memory word location remains writable, the NAND gate
40 _c operates to reset flip-flop 136. Conversely, when only one memory word location remains in a state capable of reading, NAND gate 40 _a sets the flip-flop 136 operates. Furthermore, when the last memory word locations that have been instructed is actually being or read written, both NAND gate 40 _b is operated NAN
Enable D gates 138 and 140. Both NAND gates 138,
The enable of 140 allows the flip-flop 136 to output a full or empty indication to an external device via the FULL line 20 or the EMPTY line 26.

As an example of the above, the read address ring counter stage 36
The output of ₂ is a logic 1, thus memory word location 5
0 ₂ and likewise write address ring counter stage 32
₃ it is assumed that points to the memory word locations 50 _3. This represents the state where the memory word location 50 ₂ is the last memory word written and is to be read next, i.e. almost empty. Therefore, NA
Both inputs of ND gate 40 _{a2 go} high and its output goes low.
It leads to the AND gate 41 and sets the flip-flop 136. As a result, when memory word location 50 ₃ is read, it detects that NAND gate 40 _b3 is equal between both stages 36 ₃ and 32 ₃ and enables NAND gate 138 to put an empty (EMPTY) state on output 26. Signal.

For the memory full example, the output of the write address ring counter stage 32 ₂ is a logic 1 and thus points to the memory word location 50 ₂ , and similarly the read address ring counter stage 36 ₃ points to the memory word location 50 ₃ . It is assumed that This is the memory word location
50 ₂ the last memory word read is then those are to be written state, that ho Isuzu represent full state. Therefore, both inputs of NAND gate 40 _c2 are both high and its output leads low to the reset input of flip-flop 136. The flip-flop 136 is then reset, anticipating a full condition and setting a logic high on one input of the NAND gate 140. Indeed, occurs following a write operation, write and read stage 36 _3, 32 ₃ are memory word locations 50 ₃ both
, NAND gate 40 _b3 enables NAND gate 140 and a logic low signals a FULL condition on output 20.

(Advantages of the Invention) From the above, an asynchronous FIFO buffer memory at the time of zero passage including a clear empty or full state is provided. While the comparator detects when a memory word has been written or read, the last R / W operational flip-flop maintains a determination of whether the last memory operation was a read or write operation. Read signal generators and write signal generators generate internal read and write pulses in response to the leading edge transitions of each input read and write command. The read signal generator also responds to the comparator section and the last R / W operation flip-flop, both read and write address ring counters point to the same memory word, and the last operation was a memory read operation. In addition, the internal generation of read signals is prevented. Similarly, the write signal generator is the comparator section and the last R / W.
In cooperation with the operation flip-flop, it prevents the generation of a write signal if both counters point to the same memory word and the last operation was a write operation.

According to the improved write circuit disclosed herein, both the memory write operation and the address generator increment operation are performed by the negative transition of the write clock pulse. The writing method and circuit of the present invention are advantageous in that the possibility of address conflict is eliminated and the maximum operating frequency of the FIFO memory is increased.

While the preferred embodiment of the method and apparatus of the present invention has been disclosed in relation to a particular logical structure, details of the method and apparatus of choice may be selected as a matter of engineering choice without departing from the scope of the invention as defined in the claims section. Many changes are possible. Also, it is not necessary to include all of the various advantageous features disclosed herein in a single composite FIFO memory buffer, but only to achieve the individual advantages. Such advantageous features are described in some of the following sections.

 The following items are disclosed in relation to the above description.

(1) In a method of sequentially addressing a plurality of memory registers using a write pulse including first and second transitions: incrementing a write address generator in response to the first transition of the write pulse. At the same time, in response to a first fiber of the write pulse, applying a previously stored address signal to a memory register; and in response to a second transition of the write pulse from a write address generator. Storing the address signal of the.

(2) The method of claim 1, further comprising the step of inhibiting the application of an address signal to the address register in response to the second transition of the write pulse.

(3) The method of paragraph 1, wherein the first and second transitions of the write pulse have opposite polarities.

(4) The write address generator comprises a plurality of locations including a first location and a second location, and the step of incrementing the write address generator comprises: providing a clock input to the write address generator, The method of claim 1 comprising the step of shifting a logical "1" bit from a first location to a second location.

(5) The step of applying the stored address signal comprises: responsive to a second transition of the previous clock pulse, inversion of the previously stored address signal of a NOR gate having an output connected to a memory register. Applying a first transition to a second input of a NOR gate and transferring the address signal to a memory register.

(6) In a method of incrementing an address generator that sequentially writes multiple memory registers while simultaneously storing multiple write address bits in each location connected to each latch: a positive transition edge of a clock signal. Storing an address bit in a first latch in response to a negative transition transition edge of the clock signal from a first location to a second location in response to a negative transition transition edge of the clock signal; Writing a previously stored address bit from a first latch to a memory register in response to an edge; storing an address bit in a second latch in response to a next positive transition transition edge of the clock signal; In the first latch in response to the next positive transition edge of the clock signal Step stops the writing store address bits; method provided with; and subsequent locations, latch and repeating the above steps for the memory registers.

(7) The address generator is a ring counter having first and last locations: storing address bits in the last latch in response to a positive transition transition edge; address in response to a negative transition transition edge. Incrementing a bit from the last location to a first location; and writing a previously stored address bit from a first latch to a memory register in response to a negative transition transition edge.

(8) generating the write clock pulse from the leading edge of a plurality of write command pulses;

(9) each said latch is a transparent latch: loading an address bit into a transparent latch in response to a positive transition transition edge of a clock signal; said address bit in response to a subsequent negative transition transition edge of said clock signal 7. The method of claim 6 further comprising: inverting the inversion of the transparent latch from the transparent latch to a NOR gate; and writing the address bit from an output of the NOR gate to a memory register in response to a negative transition edge of the clock signal.

(10) In a method of writing data to a plurality of memory registers in a first-in first-out memory and simultaneously applying a clock input from the first stage of the write address shift register of the memory to the next stage of the write address shift register: Forming a plurality of clock pulses each having a predetermined width and first and second transitions of opposite polarities in response to a leading edge of a successive write command; address bits in response to the second transition. In a transparent latch connected to the first stage; directing address bits to a memory register in response to a subsequent first transition; and in response to the first transition from the first stage to the next. Applying a clock input to the shift register to the stages of.

(11) The method according to item 10, wherein the first transition is a negative transition and the second transition is a positive transition.

(12) selecting a predetermined width that makes the shift register recoverable between the first transitions; and determining the maximum transmission frequency of the first-in first-out memory from the predetermined width and the time required to address the memory register. Choosing to be equal to the reciprocal of
The method of paragraph 10, further comprising:

(13) In a device for sequentially addressing a plurality of memory registers: a clock signal source operable to transmit clock pulses, each clock pulse having first and second transitions; connected to said clock signal source, An address generator operable to increment from a first address location to a next address location in response to a first transition of a clock pulse; storage means coupled to the address generator and the clock source, The storage means is operable to store an address signal in response to the second transition of the preceding clock pulse; and the address signal is added from the storage means to a memory register in response to the first transition. Device.

(14) A gate is connected to the output of the storage means, and the gate is operable to transmit the address signal to a memory register in response to the first transition.
Device of paragraph 13.

(15) The apparatus of paragraph 14, wherein the gate is operable to discontinue transmission of the address signal in response to a next second transition occurring after the first transition.

(16) The apparatus according to item 13, wherein the first transition and the second transition have opposite polarities.

(17) The interval between the second transition and the subsequent first transition is
Selected to enable recovery of the address generator during address incrementation, the clock signal source generating the clock pulse in response to a leading edge transition of a write command pulse, and the two leading edge transitions. The apparatus of paragraph 16 wherein the minimum interval between is equal to the clock pulse plus the time required for the address generator to recover.

(18) The apparatus according to item 16, wherein the first transition is a negative transition and the second transition is a positive transition.

(19) a plurality of address locations in the address generator including the first address location, the next address location and the last address location; wherein the address generator includes the address from the first address location. 14. The apparatus of claim 13, operable to sequentially increment through locations to the last address location, after which the address generator increments back to the first address location.

(20) The apparatus of paragraph 13, wherein said storage means comprises a plurality of transparent latches variously connected to respective address locations.

(21) The address generator comprises a ring counter having a first bit of one polarity at one of its locations and the remaining location contains a second bit of opposite polarity; and the development address generator is at the first transition. In response, operable to shift the first bit to an adjacent position; the apparatus of paragraph 13.

(22) A plurality of gates including a developing first gate are further provided, and the gates are respectively connected to the storage means, the clock signal source and each memory register, and the selected one of the gates is the second transition. 14. The apparatus of paragraph 13 operable to receive an inversion of the address signal from the storage means in response to, and each gate to transmit the address signal to a respective memory register in response to a first transition.

(23) In a shift register memory system having a plurality of interconnected memory registers for writing data in response to a memory operation: a plurality of writes each having a first transition and a second transition opposite the first transition. A write clock operable to generate an embedded clock pulse; a write address generator connected to the clock and having a plurality of address locations, the write address generator being responsive to the first transition; Incrementing from one address location to the next address location; a plurality of transparent latches connected to the clock and corresponding to each location in the write address generator, each latch in response to a second transition. Operable to store a write signal from a respective address location; and said clock, A plurality of gates each connected to a respective latch and a respective memory register, each gate being capable of transmitting a write signal to said memory register in response to a first transition. Register memory system.

(21) Each clock pulse is generated in response to a leading edge transition of a write command, the width of said clock pulse being determined by the amount of time required to write data into the memory register in response to the address signal. 23. The write controller of claim 23, wherein the minimum interval between any two leading edge transitions is equal to the clock pulse plus the time required for the address generator to recover between increments.

(25) The write control device according to item 23, wherein the first transition is a negative transition and the second transition is a positive transition.

(26) Read address generator for sequentially addressing each of the memory registers and reading data from the memory register; comparing the address of the write address generator with the address of the read address generator, and confirming that these two addresses are equal. A comparator for determining; a read and write storage means for storing an instruction regarding the latest read or write operation of the memory system; and a comparator for determining that the read and write addresses are equal and a final memory 23. The device according to claim 23, further comprising: a prevention device for preventing a memory operation of the memory register when the read and write storage means stores therein an instruction that the operation is a predetermined operation of the memory system. Write control device.

(27) The write address generator comprises a plurality of latches each connected to the write clock, a first address bit being stored in one of the latches, and a second address having a polarity opposite to the first address bit. 24. The write controller of claim 23, wherein address bits are stored in the rest of the latches and the address generator is responsive to a first transition to shift the first address bits into an adjacent latch.

(28) Each transparent latch has an input and an output, and each transparent latch is operable to generate an inversion of the write signal at the output in response to a first transition; A gate comprises a NOR gate operable to receive the write signal as one input thereof, the NOR gate being operable to generate the write signal at its output in response to a first transition; 23. The writing control device according to item 23.

[Brief description of drawings]

1 is a block diagram of an environment in which the present invention can be implemented; FIG. 2 is a more detailed block diagram of the present invention, showing various functional parts of a FIFO memory buffer; FIG. A simplified schematic diagram of a portion of a W / R controller using a monostable multivibrator circuit for generating write signals from edge transitions; FIG. 4 is a detailed wiring diagram of a preferred embodiment of a FIFO memory buffer; FIG. 5 is a waveform diagram of the monostable multivibrator circuit of the W / R controller; FIG. 6a is a detailed circuit diagram of the write circuit block shown in FIG. 4 based on pending US Patent Application No. 746,920. FIG. 6b is a fourth diagram according to the present invention;
FIG. 7a is a detailed circuit diagram of the write circuit block shown in the figure; FIG. 7a is a timing diagram corresponding to FIG. 6a; and FIG. 7b is a timing diagram corresponding to FIG. 6b. 10 …… FIFO memory buffer, 16,22 …… Data input, output bus, 32,36 …… Write, read address ring counter (generator), 40 …… Comparator, 48 …… Memory, 50 …… Memory Register, 60, 80 ... Write, read signal generator, 64, 84
...... Memory operation prevention device, 70 ...... Read and write storage means (last R / W operation flip-flop), 154 ... Latch (storage means), 156 ... NOR gater.

Claims (1)

(57) [Claims] 1. A method of sequentially addressing a plurality of memory registers using a write pulse including first and second transitions: Incrementing a write address generator in response to the first transition of the write pulse. At the same time, in response to the first transition of the write pulse, adding a previously stored address signal to a memory register; and in response to the second transition of the write pulse, a write address generator. To store the next address signal from.