JP3645696B2 - PCI bus / S / T interface connection device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PCI bus / S / T interface connection device for transferring data between a PCI bus of a personal computer used in an ISDN terminal adapter or the like and an SDN interface of ISDN.
[0002]
[Prior art]
Conventional ISDN terminal adapters use a low-speed interface such as RS-232C as an interface with a personal computer (hereinafter referred to as a personal computer).
[0003]
On the other hand, a terminal adapter having an interface with a PCI bus which is a standard local bus of a personal computer has been developed. In this terminal adapter, a bridge LSI having a PCI bus interface is used to interface the PCI bus with the ISDN S / T interface.
[0004]
[Problems to be solved by the invention]
The first problem of the conventional bridge LSI is that an external local memory is required, which increases the number of chips and the chip area, resulting in an increase in product cost.
[0005]
The reason is that the interface to the PCI bus inside the bridge LSI is performed only by the PCI target function, and therefore data framing is performed when transferring data between the high-speed PCI bus and the low-speed ISDN S / T interface. This is because it is necessary to temporarily accumulate data transferred from (to) the PCI bus for speed adjustment such as data buffering and data buffering.
[0006]
Similarly, an external memory is required when the interface with the high-speed PCI bus performs normal DMA transfer without using the list method while using the PCI bus master function.
[0007]
The second problem is that a large-scale FIFO is required inside the bridge LSI, which increases the circuit scale and increases the product cost.
[0008]
The reason is the same as in the first problem.
[0009]
The third problem is that the load on the CPU and OS of the personal computer becomes heavy.
[0010]
The reason for this is that the interface to the PCI bus inside the bridge LSI is performed by the PCI target function, so that the CPU and OS on the personal computer side perform all the transfer control and interrupt each time the transfer ends. This is because it is necessary to perform processing.
[0011]
Also, even when normal DMA transfer is performed while the PCI master function is used as an interface with the PCI bus in the bridge LSI, it is necessary to perform interrupt processing every time transfer is completed. It is.
[0012]
The object of the present invention is to reduce the large-scale FIFO and external local memory, which have been necessary in the past, when interfacing between the PCI bus and the ISDN S / T interface. An object of the present invention is to provide a PCI bus / S / T interface connection device that reduces the load on the OS, speeds up the execution of an application, and improves the operability of a personal computer user.
[0013]
[Means for Solving the Problems]
The PCI bus / S / T interface connecting device of the present invention is a device for transferring data between a PCI bus, which is a standard high speed local bus of a personal computer, and a low speed interface such as an ISDN S / T interface , A PCI bus master function, a PCI target function, a PCI parity function, a PCI configuration register, a PCI status register, a PCI interface unit for interfacing with the PCI bus, and a transmission / reception DMA unit for DMA transfer as a PCI bus master; An internal register having at least a DMA control / status register, an S / T interface LSI interface unit that interfaces with the S / T interface LSI, a transmission FIFO and a reception FIFO for storing transfer data Is composed of a, by the PCI bus master function, the loaded from the main memory of the personal computer, transfer start address, a transfer end address, the current transfer pointer, the data transfer amount, the frame end signal, the presence or absence of the next data transfer, the following Transfer descriptor for which the transfer list pointer is described, transfer start address, transfer end address, current transfer pointer, frame end signal, presence / absence of next data transfer, transfer for reception in which the next transfer list pointer is described based on the descriptor, from the so as to personal computers and the data transfer, a main memory of the personal computer based on the transfer descriptor pointer which is previously set in the DMA control / status register receives a transmission command from said personal computer Means for DMA-reading the transfer descriptor for transmission and storing it in the DMA control / status register, and data designated by the current transfer pointer described in the transmission transfer descriptor stored in the DMA control / status register Is read from the main memory and stored in the transmission FIFO, and when the transmission FIFO is full, the current transfer pointer is updated and the DMA is written to the transmission transfer descriptor to complete the data transfer. And when a reception request is received from the personal computer during the data transfer, the remaining data transfer is suspended after waiting for the completion of the transfer of the data currently being transferred, and the transmission transfer descriptor before the suspension is DMA-written. Information in the middle of the transfer, and When the transmission descriptor has been stored in the DMA control / status register, the remaining suspended data transfer is resumed, and when the transfer of the data transfer amount described in the transmission transfer descriptor is completed, the transmission transfer is completed. Means for setting a next transmission transfer descriptor pointer described in the descriptor in the DMA control / status register, and corresponding data when the next transmission transfer descriptor pointer is set in the DMA control / status register. And means for interrupting transmission to the CPU of the personal computer when the next transmission transfer descriptor pointer is not set.
[0019]
As described above, information on data to be transferred and actual data are stored in the main memory, and data to be transferred from the main memory by a list type DMA method using a transfer descriptor at the time of data transfer with the PCI bus. By transferring the information and the actual data, a large-scale FIFO or local memory for temporarily storing the transfer data becomes unnecessary.
[0020]
Further, since the next transfer information can be included in the transfer descriptor, continuous transfer is possible. Therefore, it is not necessary for the CPU to perform an interrupt process every time transfer is completed, and the load on the CPU is reduced and the CPU can perform other operations. As a result, the execution of the application becomes faster and the operability of the personal computer user is improved.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
FIG. 1 is a block diagram showing an embodiment of a PCI bus / S / T interface connecting apparatus according to the present invention.
[0023]
A PCI bus / S / T interface connection device 10 shown in FIG. 1 includes a PCI interface unit 11, a transmission / reception DMA unit 12, an internal register 13, an S / T interface LSI interface unit 14, a transmission FIFO 15, The reception FIFO 16, the transmission HDLCs 17 and 18, the transmission RA 19, the reception HDLCs 20 and 21, and the reception RA 22.
[0024]
The PCI interface unit 11 has a PCI master function, a PCI target function, a PCI parity function, a PCI configuration register, a PCI status register, and the like, and performs an interface with the PCI bus.
[0025]
The transmission / reception DMA unit 12 performs DMA transfer based on the setting of the internal register. The internal register 13 includes a DMA control / status register, an HDLC control / status register, an RA control / status register, an asynchronous communication control / status register, a D channel control / status register, and an S / T interface LSI control / status register. (Both not shown).
[0026]
The S / T interface LSI interface unit 14 interfaces with an existing S / T interface LSI (not shown) of ISDN. The transmission FIFO 15 and the reception FIFO 16 accumulate the minimum data necessary for transmission / reception (corresponding to the amount of time that is awaited by performing DMA as a PCI master).
[0027]
The transmission HDLCs 17 and 18 create HDLC frames at the time of transmission, and the reception HDLCs 20 and 21 create information data from the HDLC frames at the time of reception. The transmission RA 19 and the reception RA 22 are asynchronous communication V.16. 110 is supported.
[0028]
The PCI bus / S / T interface connecting apparatus 10 uses a list-type DMA (Direct Memory Access) for data transfer. This list method uses a transfer descriptor (TD: Transfer Descriptor) shown in FIGS. FIG. 2 is a diagram showing a transfer data descriptor for transmission, and FIG. 3 is a diagram showing a transfer data descriptor for reception.
[0029]
The transmission transfer descriptor includes a TSP (Transfer Start Pointer) that describes a transfer start address (SA), a TEP (Transfer End Pointer) that describes a transfer end address (EA: End Address), and the current transfer. A CBP (Current Buffer Pointer) describing a pointer, a TC (Transfer Count) describing a data transfer amount, an FE (Frame End) describing a frame end signal, and an NT (Description) describing the next data transfer information Next Transfer) and an NTDP (Next Transfer Descriptor Pointer) describing the next transfer list pointer. For transferring transmit data between the TD (transfer descriptors) PC based on the. TD is set for each transmission channel.
[0030]
The reception transfer descriptor includes a TSP (Transfer Start Pointer) describing a transfer start address (SA), a TEP (Transfer End Pointer) describing a transfer end address (EA: End Address), and the current transfer. A CBP (Current Buffer Pointer) that describes a pointer, an FE (Frame End) that describes a frame end signal, an NT (Next Transfer) that describes next data transfer information, and a next transfer list pointer The transmission / reception DMA unit 12 transfers received data to and from the personal computer based on this TD. The transmission / reception DMA unit 12 is composed of an NTDP (Next Transfer Descriptor Pointer). Note that TD is set for each reception channel.
[0031]
Next, a transmission operation by DMA transfer will be described with reference to FIGS. 4 and 5 together with FIG. FIG. 4 and FIG. 5 are transmission flowcharts of the DMA transfer method.
[0032]
Data transmission by DMA starts by writing a transmission command to the DMA control / status register. When the transmission command is accepted (step S101 in FIG. 4), the transmission / reception DMA unit 12 (see FIG. 1) loads TD (DMA read) from the main memory (not shown) on the personal computer side and starts data transfer (see FIG. 1). S102).
[0033]
This data transfer is performed as follows.
The PCI bus / S / T interface connecting apparatus 10 determines the transfer enable state (step S201 in FIG. 5), and the transfer descriptor pointer (TD pointer) stored in the DMA control / status register of the internal register 13 at the time of initialization. 2 is loaded (DMA read) from the main memory on the personal computer side and stored in the DMA control / status register (S202).
[0034]
The transmission / reception DMA unit 12 determines whether or not the storage capacity of the FIFO 15 has a margin, and when there is a margin, performs a DMA read based on the TD stored in the DMA control / status register and stores the data in the FIFO.
[0035]
When the FIFO 15 is full (S203), the current transfer pointer (CBP) is updated (S205), and the transfer of data written to the TD (DMA write) is terminated (S206). At this time, another channel is transferred.
[0036]
If there is a reception request during data transfer (S103), the transfer of data that is currently being transferred is waited for completion (S104), the transfer of the remaining data is temporarily suspended (S105), and the data is being transmitted (before being temporarily interrupted). The TD of) is DMA-written to hold the data being transferred, and the TD requested to be received is DMA-read and stored in the DMA control / status register (S106). At this time, another channel is transferred.
[0037]
When storage of the TD requested to be received in the DMA control / status register is completed, the temporary interruption in step S105 is restored (S107), the remaining data transfer is resumed (S108), and the completion of the data transfer is monitored. . When the transfer of the amount described in TD is completed (S109), the next TD pointer (NTDP) described in TD is set in the DMA control register.
[0038]
Receiving DMA unit 12 searches whether DESCRIPTION NTDP indicating the next transmission list in the DMA control / status register in the register 1 3 (S110), when NTDP is described, designated by NTDP returns to step S102 Starts transferring the transferred data.
[0039]
Since the next transfer is started by the TD pointer set in the DMA control register in this way, continuous transfer is possible.
[0040]
When NTDP indicating the next transmission list is not described in the TD stored in the DMA control register, a transmission end interrupt is issued to the CPU on the personal computer side (S111).
[0041]
Next, a reception operation by DMA transfer will be described with reference to FIGS. 6 and 7 together with FIG. 6 and 7 are reception flowcharts of the DMA transfer method.
[0042]
When the reception is enabled (step S301 in FIG. 6), the reception data stored in the reception FIFO is transferred to the main memory on the personal computer side (S302).
[0043]
This data transfer is performed as follows.
The receiving FIFO 16 is searched to detect the presence or absence of received data (step S401 in FIG. 7). The reception FIFO 16 stores data corresponding to the amount of data set in the DMA control / status register.
[0044]
When reception data is stored in the reception FIFO 16, the TD shown in FIG. 3 is loaded (DMA read) from the main memory based on the TD pointer stored at the time of initialization in the DMA control / status register (S402). Based on the TD, the data in the reception FIFO is stored in the main memory on the personal computer side (DMA write) (S403).
[0045]
When the DMA write of the amount set in the TD stored in the DMA control / status register is completed, the current transfer information (CBP) is updated (S404), written to the TD (DMA write), the current transfer is terminated, and the data Waits until it is stored in the FIFO (S405). At this time, another channel is transferred.
[0046]
During this data transfer (S302), the storage of the received data to be transferred is monitored in the main memory on the personal computer side, and the received data is stored in the main memory on the personal computer side until the TD transfer end pointer (S303). The next described TD pointer (NTDP) is set in the DMA control register.
[0047]
Receiving DMA unit 12 searches the presence or absence of the setting of the NTDP that the DMA control / status register in the register 1 3 shows the next reception list (S304), when NTDP is described, designated by NTDP returns to step S302 The next transferred TD is loaded to start data transfer, and data transfer is continued continuously.
[0048]
When NTDP is not described in the DMA register control / status register,
A reception error occurs (S305), and an interrupt is generated for the CPU on the personal computer side (S306).
[0049]
【The invention's effect】
As described above, the PCI bus / S / T interface connecting device of the present invention has a PCI bus master function, and when performing data transfer by DMA transfer by a list method, a transfer descriptor describing various information related to transfer data is provided. By using it, it is possible to store data transfer information and data itself in the main memory on the personal computer side. Therefore, the first effect is that an external local memory and a large-scale FIFO are not required, and it is inexpensive. The system can be configured.
[0050]
The second effect is that continuous data transfer is possible by list-type data transfer, so that it is not necessary to cause the CPU on the personal computer side to perform interrupt processing every time one transfer is completed as in the prior art. The load on the CPU and OS can be reduced.
[0051]
The third effect is that the load on the CPU and OS can be reduced, so that the execution of the application can be accelerated and the operability of the personal computer user can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a transmission transfer data descriptor according to the present invention.
FIG. 3 is a diagram illustrating a configuration of a transfer data descriptor for reception according to the present invention.
FIG. 4 is a transmission flowchart of the DMA transfer method of the present invention.
FIG. 5 is a detailed transmission flowchart of the DMA transfer method of the present invention.
FIG. 6 is a reception flowchart of the DMA transfer system of the present invention.
FIG. 7 is a detailed reception flowchart of the DMA transfer system of the present invention.
[Explanation of symbols]
10 PCI Bus / S / T Interface Connection Device 11 PCI Interface Unit 12 Transmit / Receive DMA Unit 13 Internal Register 14 S / T Interface LSI Interface Unit 15 Transmission FIFO
16 Receive FIFO
17 Transmission HDLC
18 Transmission HDLC
19 Transmitting RA
20 HDLC for reception
21 HDLC for reception
22 RA for reception

Claims (1)

An apparatus for transferring data between a PCI bus, which is a standard high-speed local bus of a personal computer, and a low-speed interface such as an ISDN S / T interface,
A PCI bus master function, a PCI target function, a PCI parity function, a PCI configuration register, a PCI status register, a PCI interface unit for interfacing with the PCI bus, and a transmission / reception DMA unit for DMA transfer as a PCI bus master; An internal register including at least a DMA control / status register, an S / T interface LSI interface unit that interfaces with the S / T interface LSI, a transmission FIFO and a reception FIFO for storing transfer data,
The PCI bus master function loads the transfer start address, transfer end address, current transfer pointer, data transfer amount, frame end signal, presence / absence of next data transfer, and next transfer list pointer loaded from the main memory of the personal computer. Based on the described transfer descriptor for transmission, transfer start address, transfer end address, current transfer pointer, frame end signal, presence / absence of next data transfer, and transfer descriptor for reception in which the next transfer list pointer is described To transfer data with the personal computer ,
Upon receiving a transmission command from the personal computer, the transmission transfer descriptor for DMA is DMA-read from the main memory of the personal computer based on a transfer descriptor pointer preset in the DMA control / status register, and stored in the DMA control / status register. Means to
Means for DMA-reading the data specified by the current transfer pointer described in the transmission transfer descriptor stored in the DMA control / status register from the main memory and storing the data in the transmission FIFO;
Means for updating the current transfer pointer when the transmission FIFO becomes full, DMA writing to the transmission transfer descriptor, and ending data transfer;
When there is a reception request from the personal computer during the data transfer, the transfer of the data currently being transferred is awaited, the remaining data transfer is temporarily suspended, and the transmission transfer descriptor before the temporary suspension is DMA-written and the transfer is in progress When the reception transfer descriptor for which the reception request has been received is stored in the DMA control / status register, the temporarily suspended remaining data transfer is resumed, and is described in the transmission transfer descriptor. Means for setting the next transmission transfer descriptor pointer described in the transmission transfer descriptor in the DMA control / status register when the transfer of the data transfer amount is completed;
When the next transmission transfer descriptor pointer is set in the DMA control / status register, the corresponding data is transferred, and when the next transmission transfer descriptor pointer is not set, the data is transmitted to the CPU of the personal computer. A means to interrupt termination,
A PCI bus / S / T interface connection device comprising:

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