JP2504511B2 - DMA controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A DMA controller for performing message communication between bus masters of each bus in a system having a plurality of buses is provided for each of the plurality of buses in order to reduce the number of hardware when designing the system. A peripheral controller provided by being connected to each of the plurality of buses in a system to which a bus master is connected, the message controller storing a message from each of the plurality of bus masters, and a single controller in response to a request from each of the plurality of bus masters. A message between the plurality of bus masters, which has access control means for allowing one bus master to access the message buffer, and notification means for notifying the bus master that is the destination of the message that the message has been stored in the message buffer. Configure to communicate.

[Industrial applications]

The present invention relates to a DMA controller, and more particularly to a DMA controller that performs message communication between bus masters of each bus in a system having a plurality of buses.

In a system having a plurality of buses, there is a system that manages each bus by providing a bus master for each of the plurality of buses. In this case, message communication is required between each bus master in order to adjust the operation of the entire system.

[Conventional technology]

Conventionally, in a system in which bus masters 11 and 21 and peripheral controllers (that is, DMA controllers) 12 and 22 are connected to buses 10 and 20 respectively as shown in FIG. 7 (A), first-in first-out circuits (FIFO) 15 and 16 Bus master installed between 10 and 20
Store the messages from 11,21 respectively in FIFO15,16 respectively,
The bus masters 21 and 11 read out each of them to perform message communication.

Further, as shown in FIG. 9B, a dual port RAM 17 is provided instead of the FIFOs 15 and 16, and the bus masters 11 and 21 access the dual port RAM 17 to perform message communication.

[Problems to be Solved by the Invention]

In the above conventional system, an external circuit for notifying the bus masters 11 and 21 that the message has been written to each of the FIFOs 15 and 16 or the dual port RAM 17 must be added, which increases the number of system hardware points and complicates the system design. There was a problem of becoming.

The present invention has been made in view of the above points, and an object of the present invention is to provide a DMA controller that reduces the number of hardware when designing a system.

[Means for solving the problem]

FIG. 1 shows a principle block diagram of the DMA controller of the present invention.

In the figure, the bus masters 26a and 26b are provided for the multiple buses 25a and 25b, respectively.
The peripheral controller 27 is connected to each of the buses 25a and 25b.

In the peripheral controller 27, a message buffer 27a,
Access control means 27b and notification means 27c are provided.

The message buffer 27a stores messages from each of the plurality of bus masters 26a and 26b.

Further, the access control means 27b includes a plurality of bus masters 26a, 2a.
A single bus master is made to access the message buffer 27a in response to access requests from the respective 6b.

The notification means 27c notifies the bus master 26b which is the destination of the message that the message from one of the bus masters (for example, 26a) is stored in the message buffer 27a.

[Action]

In the present invention, in addition to the message buffer 27a in the DMA controller 27, access control means 27b and notification means
27c is provided, and message communication between the bus masters 26a and 26b can be performed only by connecting the peripheral controller 27 to the plurality of buses 25a and 25b, and it is not necessary to add an external circuit. This does not increase the hardware score.

〔Example〕

FIG. 2 shows a system configuration diagram of an embodiment of a 2-bus system to which the DMA controller of the present invention is applied.

In the figure, a bus 30 is an address bus 30a, a data bus 30b,
The control bus 30c is composed of a CPU 31, a bus master CPU 31, an I / O interface 32, and a memory 33. Similarly, the bus 40 is composed of an address bus 40a, a data bus 40b, and a control bus 40c. The bus 40 includes a CPU 41 as a bus master and an I / O.
The interface 42 and the memory 43 are connected to each other.

The DMA controller 50 is directly connected to the controller buses 30C and 40c, is also connected to the address buses 30a and 40a through the bidirectional buffers 51a and 51b, and similarly is also connected to the data bus 30b through the bidirectional buffers 52a and 52b. , 40b, respectively.

The buffers 52a and 52b have a control signal DBEN for switching the buffer on / off from the DMA controller 50 to the terminal EN.
1, DBEN2, respectively, and control signals DIN1, DIN2 for switching the signal direction are supplied to the terminal T / R. Thereby, the data bus 30b and the data input / output terminal of the DMA controller 50, the data bus 40b and the input / output terminal of the DMA controller 50, or the data buses 30b and 40b can be connected.

Each of the buffers 51a and 51b has exactly the same configuration as the above-mentioned buffers 52a and 52b, and the terminal EN is supplied with control signals ABEN1 and ABEN2 for switching on / off from the DMA controller 50 and the signal direction is switched to the terminal T / R. Control signals AIN1 and AIN2 are supplied.

FIG. 3 shows a block diagram of an embodiment of the DMA controller 50.

In the figure, the transfer request control unit 70 includes an I / O interface 32,
42, transfer request signals REQO to REQ3 coming in to the terminal 71 via the control buses 30c and 40c are supplied from the memories 33 and 34, respectively. The transfer request control unit 70 selects a single transfer request signal according to a predetermined priority order and reports it to the central processing unit 72 and the operation determining unit 73 even if there are a plurality of transfer requests at the same time.
The operation determining unit 73 responds to this report.

Slave control unit 7 which is access control means 27b in FIG.
The CPU 31 and 41 are respectively supplied with chip select signals CS1 and CS2 and interrupt request response signals IACK1 and IACK2 coming into the terminals 75 and 76 via the control buses 30c and 40c, respectively. The chip select signal is a signal for each of the CPUs 31 and 41 to access (slave access) the register 77 or the communication register 91 described later, and the interrupt request response signal is
When the DMA controller 50 makes an interrupt request to each of the CPUs 31 and 41, it is a signal that the CPUs 31 and 41 respond to for slave access. The slave controller 74 selects a single signal according to a predetermined priority order and reports it to the operation determiner 73 even if these signals are present at the same time.

In response to this report, the operation determination unit 73 responds to the slave control unit 74 with a response indicating whether slave access is possible, transmits the report from the slave control unit 74 to the central processing unit 72, and further from any of the buses 30 and 40. A bus attribute signal indicating whether it is a slave access or not is supplied to the communication register 91. The slave control unit 74 which has received a response from the operation determination unit 73 that the slave access is possible generates a read request signal or a write request signal and supplies the read request signal or the write request signal to the central processing unit 72 and the communication register 91.

The central processing unit 72 manages the operation state of the entire DMA controller 50, and the operation state and the operation request are the operation determination unit.
Reported to 73. Register 77 built in the central processing unit 72
The transfer source address, destination address, number of blocks, and the like are stored in.

When the central processing unit 72 requests the bus right, the operation determining unit 73 gives an instruction to the bus right control unit 80. As a result, the bus control unit 80 sends the bus right request signal HREQ1,
Supply HREQ2. On the other hand, the bus right request response signals HACK1 and HACK2 output by the CPUs 31 and 41 respectively come in from the terminal 82, and the bus right control unit 80 reports the arrival of the signals HACK1 and HACK2 to the operation determining unit 73. This report is transmitted to the central processing unit 72.

The terminal control unit 83 is supplied with the data complete signals DC1 and DC2 indicating the completion of the writing / reading of the data coming from the control buses 30c and 40c, respectively, to the terminal 84, and reports this to the operation determining unit 73 and also determines the operation. The data complete signal DC from the terminal 84 is output according to an instruction from the unit 73.
Similarly, the read / write signals R / W1 and R / W2 supplied from the terminal 85 are reported to the operation determining unit 73, and
Signal address strobe signal according to the instruction from the operation decision unit 73
AS1, AS2, data strobe signals DS1, DS2 and read / write signals R / W1, R / W2 are output from terminal 85, respectively. Furthermore,
From the terminal 86 to the buffers 51a to 52b according to an instruction from the operation determining unit 73.
Control signals AIN1, AIN2, ABEN1, ABEN2, DIN1, respectively
DIN2, DBEN1 and DBEN2 are supplied, and the data transfer acknowledge signals ACK0 to ACK3 are output from the terminal 94.

The input / output control unit 87 supplies the address coming from the buffers 51a and 51b to the terminal 88 to the register 77 and the communication register 91 of the central processing unit 72 via the internal address according to the instruction of the operation determining unit 73, and at the same time, the central processing unit. The address from 72 is supplied from the terminal 88 to each of the buffers 51a and 51b. Further, the data coming from the buffers 52a and 52b to the terminal 89 is supplied to the register 77 and the communication register 91 via the internal data bus, and the data from the register 77 or the communication register 91 is supplied from the terminal 89 to the buffers 52a and 52b. To do. Further, the data holding register 90 built in the input / output control unit 87 stores transfer data at the time of dual transfer.

The communication register 91 has the structure shown in FIG. An address is supplied to the decoder 101 from the internal address bus 102, a read request signal and a write request signal from the slave control unit 74 are supplied via the terminals 103a and 103b, and an operation determining unit 73 is supplied via the terminal 104. Bus attribute signals are supplied. The decoder 101 decodes these and supplies a read enable signal and a write enable signal to the message buffer 105 which is the message buffer 27a in FIG. 1 and the status buffer and interrupt generation circuit 106 which is the notifying means 27c.

The message buffer 105 is connected to the internal data bus 107, and writes and reads a message from the CPU 31 or 41 according to the write enable signal and the read enable signal.

The status buffer and interrupt generation circuit 106 is connected to the internal data bus 107 and has the configuration shown in FIG. In the figure, the LCCR buffer 110 is controlled by the CPU 31 to control bits LIEN, LICN, SINT and 4-bit status LPS.
Is written to the SCCR buffer 111 from the CPU 41 to control bits SIEN, SICL, LINT and 4-bit status SPS.
Is written. Control bits above LIEN, SIEN
Is interrupt enable, LINT and SINT are interrupt requests, and LICL and SICL are interrupt clears that clear interrupt requests.

The LCSR buffer 112 is read from the CPU 31, and the SCSR buffer 113 is read from the CPU 41. The control bit SIEN and status SPS of the LCSR buffer 112 are set to the corresponding contents of the SCCR buffer 111, and the control bit LIST is the control bit LIN of the SCCR buffer 111.
Control bit of LCCR buffer 110, set by T
It is cleared by LICL, and the interrupt status bit SIST
The corresponding contents of SCSR buffer 113 are set. SCSR
On the contrary, the buffer 113 has the same settings as the contents of the LCCR buffer 110 and the SCCR buffer 111.

The AND circuit 114 is a control bit LIEN of the LCCR buffer 110 and an interrupt status bit LIS of the LCSR buffer 112.
An interrupt request signal for the CPU 31 is generated from T and the AND circuit 115 outputs the control bit LIEN of the SCCR buffer 111.
Interrupt status bit SIST of SCSR buffer 113 and C
The interrupt request signals for the PU 41 are generated, and these interrupt request signals are supplied from the terminal 107 in FIG. 4 to the interrupt control unit 92 shown in FIG.

Also, the LCVR buffer 116 and SCVR buffer 117 each have a CP.
An interrupt vector for each of U31 and 41 is stored, and this interrupt vector is read out to each of CPU31 and 41.

Returning to FIG. 3, the interrupt control unit 92 is supplied with the interrupt request signal for data transfer supplied from the central processing unit 72 and the interrupt request signal for communication supplied from the communication register 91, and the CPU 31
And an interrupt request signal for the CPU 41 are generated and output from the terminal 93.

Here, for example, the CPU 31 sets a message in the message buffer 105, sets the control bit SINT of the interrupt request of the LCCR buffer 110, and makes an interrupt request to the CPU 41. At this time, the CPU 41 causes the SCCR buffer 111
If the interrupt enable control bit SIEN is set, the AND circuit 115 outputs an interrupt request signal, and the CPU 41 is notified of the interrupt request via the interrupt control unit 92.

When the CPU 41 receives the interrupt request, it asserts (sets true) the interrupt request response signal IACK2 and executes the interrupt acknowledge cycle. At this time, the interrupt vector of the SCVR buffer 117 is supplied to the CPU 41.

As a result, the CPU 41 reads the contents of the SCSR buffer 113 to know that there is an interrupt from the CPU 31, and also knows from the contents of the status LPS that the CPU 31 requests reception of a message. As a result, the CPU 41 reads the message buffer 105 and receives this message.

After this, the CPU 41 sets the interrupt clear control bit SICL of the SCCR buffer 111 to set the LCSR buffer 112 and SCR buffer.
The interrupt status bit SIST of the CSR buffer 113 is cleared and the normal processing is started.

Message communication from the CPU 31 to the CPU 41 is performed by the series of operations described above.

Further, various signals during slave operation for accessing the register 77 of the DMA controller 50 or the communication register 91 from the CPUs 31 and 41 will be described.

The clock C shown in FIG. 6 (A) is supplied to the DMA controller 50.
LK is supplied. At the time of reading, the CPU 31 supplies the L-level chip select signal CS1 shown in FIG. 9 (J) to the DMA controller 50 in the slave mode, and in cycle Ts ₁ , the control signal ABEN1, shown in FIGS. Same figure from CPU31 with AIN1 as L level (F)
Take in the address shown in. Further, the control signal DBEN1 shown in FIG. 6D is set to L level in cycle Ts ₄ by the H level read / write signal R / W1 shown in FIG. 7G (the signal DIN1 is set to H level as shown in FIG. level). As a result, the data shown in (H) of the figure read from the communication register 91 is output, and further the data complete signal DC1 shown in (I) of the figure is output.

At the time of writing, as shown in (K) to (S) of the figure, the control signal is generated by the read / write signal R / W1 of L level
Each of DBEN1 and DIN1 becomes L level, and the data supplied from the CPU 31 is written to the address supplied from the CPU 31 of the register 77 or the communication register 91.

As described above, since the DMA controller 50 is provided with the slave controller 74 which is the access control means 27b and the status buffer and the interrupt generation circuit 106 which is the notification means 27c in addition to the message buffer 105, only the DMA controller 50 is provided. Message communication can be performed between the CPUs 31 and 41 without adding an external circuit, the number of hardware is small, and the system design is easy.

〔The invention's effect〕

As described above, according to the DMA controller of the present invention, it is not necessary to add an external circuit, the number of hardware is small, the system design becomes easy, and it is extremely useful in practice.

[Brief description of drawings]

1 is a block diagram of the principle of the DMA controller of the present invention, FIG. 2 is a block diagram of an embodiment of a system using the DMA controller of the present invention, FIG. 3 is a block diagram of the DMA controller of FIG. FIG. 4 is a block diagram of a communication register, FIG. 5 is a configuration diagram of a status buffer and an interrupt generation circuit, FIG. 6 is a signal waveform diagram during slave operation of the system of FIG. 2, and FIG. It is a block diagram. In the figure, 25a, 25b, 30 and 40 are buses, 26a and 26b are bus masters, 27 is a peripheral controller, 27a and 105 are message buffers, 27b is access control means, 27c is notification means, 31 and 41 are CPUs, 32, 42 is
I / O interfaces, 33 and 43 are memories, 50 is a DMA controller, 51a, 51b, 52a and 52b are buffers, 70 is a transfer request control unit, 72 is a central processing unit, 73 is an operation determining unit, and 74 is a slave control unit. , 77 is a register, 80 is a bus right control unit, 83 is a terminal control unit, 87 is an input / output control unit, 91 is a communication register, 92 is an interrupt control unit, and 106 is a status buffer and an interrupt generation circuit.

Claims (1)

(57) [Claims] 1. A system in which bus masters (26a, 26b) are connected to a plurality of buses (25a, 25b), respectively.
5b) Peripheral controllers (2
7) a message buffer (27a) for storing messages from each of the plurality of bus masters (26a, 26b) and a single bus master in response to a request from each of the plurality of bus masters (26a, 26b) An access control means (27b) for accessing the message buffer (27a), and a notification means (27c) for notifying the bus master, which is the destination of the message, that the message is stored in the message buffer (27a). A DMA controller characterized by performing message communication between the plurality of bus masters (26a, 26b).