JPS6027058B2 - Interrupt control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control circuit in a processor that executes interrupt response processing with reference to reference data for an interrupt signal.

As is well known, microprocessors that are becoming popular these days are equipped with an interrupt signal input terminal, and by applying an interrupt signal to this terminal from an external device, it is possible to temporarily suspend arithmetic processing on the microprocessor side. It is configured to be changeable, and by providing reference data at the same time as the interrupt signal, it is configured to refer to this reference data and vary the contents of the interrupt response.

For example, the microprocessor PD780 (manufactured by NEC Corporation) responds to the interrupt as described above in mode 2 interrupt mode. In such a microprocessor interrupt control circuit, when an interrupt is generated from an external device, the reference data is stored in advance in a memory or the like,
Thereafter, an interrupt signal is given to the microprocessor, and the reference data is transferred to the microprocessor in response to an interrupt permission signal or data request signal from the microprocessor.

However, when there are multiple external devices as sources of interrupt signals, the microprocessor must detect which external device has generated the interrupt signal, resulting in a slow interrupt response. .

Furthermore, even if there is only one external device, transfer data unrelated to interrupt response processing, such as status data, may be transferred from the external device to the microprocessor.
If the transfer data in this case and the reference data at the time of an interrupt are transferred through separate paths, a problem arises in that the connection relationship between the microprocessor and the external device becomes complicated.

The present invention was made to solve these problems, and its purpose is to enable high-speed interrupt response, and to transfer data transferred in normal mode and reference data in interrupt mode to the microprocessor side with a simple configuration. An object of the present invention is to provide an interrupt control circuit that can transfer data to other sources.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of the present invention, in which transfer data and reference data at the time of interrupt response are transferred from a single external device to a microprocessor.

In this embodiment, the external device itself is also constituted by a microprocessor having an interrupt response function, and bidirectional data transfer is possible between these two microprocessors. Hereinafter, one microprocessor serving as an external device will be referred to as a slave processor, and the other one will be referred to as a master processor. In FIG. 1, the master processor 1 is composed of, for example, a French PD780 (manufactured by NEC Corporation), and has 16
Bit address bus output (to A, 5), 8-bit data bus input/output (Do to ○7), interrupt signal input (T), data request signal output (RD), input/output request signal output ( 10RQ), a first mine cycle signal output (skin), a data write signal output (WR), etc., and an input/output request signal 10RQ and a first machine cycle signal M
, are logically ANDed in the OR gate 2 and output as an interrupt enable signal T.ACK for the interrupt request signal mT.

Further, the input/output device number given by the lower 8-bit address signal in the address path output (Ao to A, 5) is decoded by the decoder 3 on the condition that the input/output request signal 10RQ is output, and the input/output device number is decoded by the chip. It is output as a select signal CS. In addition,
The master processor 1 has signal input/output other than the above-mentioned signals, but those not used in this embodiment are described in the "Yama COM-82 User's Manual" published by NEC Corporation (Document number mm-61 group). Since it is described in and is well known, the detailed explanation here will be omitted. Next, the slave processor 4 is, for example, a mu PD8049 (manufactured by NEC Corporation).
Two 8-bit input/output ports P
1 and P2, and the input/output port PI outputs data to be transferred to the master processor side.

Then, when a signal is input to the terminal (TO), the sending of the transfer data is stopped. In addition, a strobe signal ST is sent from the input/output boat P2 for storing the transferred data in the programmerful peripheral interface 5.
It outputs an acknowledge signal ACK indicating that it has received transfer data from master processor B and master processor 1, and an interrupt signal INT to master processor 1. Note that these signals STB, ACK, and INT are outputted via the input/output expansion unit 6. Further, when this slave processor 4 is given an interrupt signal INrs, it performs an interrupt response process for fetching the data transferred from the master processor 1 to the programmerful vertical interface 5 and stored therein. The programmable vertical interface (hereinafter referred to as PPI) 5 is
For example, it is composed of French PD8255 (manufactured by NEC Corporation),
It has three programmable input/output ports PA, PB, and PC as shown in Table 1 below, and is used as an input/output boat in state 8 of mode 2, that is, as a bidirectional input/output boat. A part of the boat PC is used in mode 2 as a signal input/output boat for controlling data transfer.

Table 2 shows the input/output signals of the boats PA to PC in the mode 2 state. Further, this PP15 has input/output terminals for a data write signal WR, a data read signal RD, a boat designation signal AI, and an AO chip select signal CS, and a boat PA is selected by setting both the signals AI and AO to "0". Ru. However, in this embodiment, in the normal mode, address signals A, . 0
" signal is input. On the other hand, mode 2 is selected by setting the 8-bit control world from master processor 1. In this case, the transfer data from master processor 1 including the control world is written. is performed by the data write signal WR, and reading of the transfer data from the stripe processor 4 and the status data of the PP 15 is performed by the data output signal RD. ,ACK, 田F,S
Of TB and INTR, the signal INTR is not used.

Further, the signal IBF is a signal indicating that the data transferred from the slave processor 4 is stored in the input/output port PA and has not yet been output from the master processor 1, and is a data output signal from the master processor 1. When the logic of the stored data is completed by RD, it returns to the "0" level. This "0" level signal IBF is input to the terminal (TO) of the slave processor 4, and thereby the slave processor 4 stops sending the transfer data to the input/output port PA. Further, the signal OBF is a signal indicating that the transfer data from the master processor 1 is stored in the input/output port PA, and this signal OBF is given to the slave processor 4 as an interrupt signal INTs. For detailed operation of this PP15, please refer to "How to use PP8255" published by NEC Corporation.
(Document number: mm Ichiro 7A) and is publicly known,
The explanation here will be omitted. Next, the selector 7 outputs a data output signal RD and an address signal A in the normal mode.
I and A0, select chip select signal CS and PP
In the interrupt mode from the slave processor 4 to the master processor 1, the interrupt enable signal INT/AC from the master processor 1 is supplied in place of the data read signal RD.
K, and AI="0", AO="0", CS="0"
The signals are supplied to the input terminals RD, AI, A0, and CS of PP15.

The switching control in this case is performed by the output signal of the OR gate 8. That is, a signal CS obtained by inverting the chip select signal CS output from the decoder 3 by an inverter 9 is input to the OR gate 8, and an interrupt signal INTs from the input/output expansion unit 6 to the master processor 1 is input. As a result, when the signal CS="1" and the signal INTs="0",
In other words, under the condition that the chip select signal CS of "0" is not output from the master processor side, the interrupt signal INT
When s occurs, the signal river T・ACK, AI of the A side input:
It is switched to select "0", AO="0", and CS="0". Also, when the chip select signal CS from the master processor side is CS="0", and when the interrupt signal state Ts from the slave processor 4 side is "1", the B side input signal RD. It can be switched to select AI, A0, and CS. In the above configuration description, the overline attached to the signal name indicates that it is significant at the "0" level. In the above configuration, in the initial state, a control world is set from the master processor 1 to the PP15 in order to make the input/output boat PA of the PP15 and part of the PC function as a mode 2 bidirectional input/output boat. Ru.

Next, when the master processor 1 wants to transfer data to the slave processor side, the address bus outputs (Ao to A,
5) sends the input/output device number of the slave processor 4, causes the decoder 3 to output the chip select signal CS, supplies this chip select signal CS to the PP 15 via the selector 7, and also outputs the address signals AI, AO.
is set to "0" and PP15 is supplied.

Then, the transfer data is sent to the data bus outputs (Do to D7), and then the data write signal WR is supplied to PP15. As a result, the data transferred from the master processor 1 is stored inside the PP 15. Then, PP15
A signal OBF is output from the CPU 4, and this signal OBF is supplied to the slave processor 4 as an interrupt signal INTs. As a result, the slave processor 4 reads the transfer data from the master processor 1 stored in the PP 15 through interrupt response processing. Thereafter, the PP 15 returns an acknowledge signal ACK (signal indicating that the transfer data has been received) to the PP 15 via the input/output port P2 and the input/output expansion unit 6. As a result, the sending of the signal OBF from the PP 15 is stopped, and the transfer process of one data is completed. Next, when the slave processor 4 wants to interrupt the processing on the mask processor side, the slave processor 4 sends reference data corresponding to the interrupt request contents from the boat PI to the data bus output, and then sends this data to the data bus output. The strobe signal STB is sent to the PP via the boat P2 and the input/output expansion unit 6 in order to be stored in the PP15.
Give to 15.

Then, the reference data from slave processor 4 becomes PP
15. At this time, when the reference data is stored in the PP15, a signal IBF indicating that the stored contents have not yet been retrieved from the master processor 1 is sent back to the terminal (TO) of the PP15. As a result, the slave processor 4 stops sending the reference data from the boat PI and stops sending the strobe signal STB from the boat 2. Thereafter, the master processor 1 sends an interrupt signal . At this time, if the chip select signal CS is not output from the mask processor side, the output of the OR gate 8 will be at the "0" level. Therefore, the selector 7 is switched to a state in which it selects and outputs the A-side input. On the other hand, the master processor 1 receives an interrupt enable signal INT/AC in response to the interrupt signal INT on the slave processor side.
K is output via OR gate 2. This interrupt enable signal INT/ACK is AI=“○”, AO=''○”,
PP1 via the selector 7 along with the CS=“○” signal.
5 is input. In other words, the signal INT/ACK is PP
The signal is input to the data output signal input terminal (RD) of No. 15. As a result, the reference data stored in the PP 15 is taken by the master processor 1, and the master processor 1 executes processing corresponding to the contents of the interrupt request based on this reference data. At this time, when the reference data stored in the PP15 is taken by the master processor 1, the signal IBF output from the PP15 becomes "0", so the slave processor 4 stops sending out the interrupt signal INT. This results in
The selector 7 is returned to its initial state. Next, when sending data to the master processor side regardless of interrupt requests, P
The transfer data is stored in P15 in advance.

Then, the data output signal R from the master processor 1
D is extracted and transferred to the master processor side. Note that when the interrupt signal mT is generated from the slave processor side and the chip select signal CS of "0" is output from the master processor side, the selector 7 is not switched and the processing on the master processor side is is given priority.

As described above, according to this embodiment, data between the master processor and slave processor and reference data regarding interrupt requests from the slave processor can be transferred using a single input/output pointer interface. Furthermore, when an interrupt request occurs, the interrupt enable signal from the master processor is configured to be returned only to the source of the interrupt request by the selector, so the master processor does not need to search for the source of the interrupt request. Can respond to interrupts at high speed. Therefore, if applied to a multiprocessor system including a plurality of slave processors 4a and 4b as shown in FIG. 2, advanced processing contents can be processed at high speed. In FIG. 2, 10 is a priority control circuit that controls the priority when the interrupt signal INT from the first slave processor 4a and the interrupt signal INL from the second slave processor 4b occur simultaneously. There are two interrupt signals INT
, , INT2 occur simultaneously, only one of them is given priority and sent to the master processor 1 via the OR gate 11. In the above embodiments, the external device itself is also constituted by a microprocessor, but the present invention is not limited to this.

Furthermore, although a programmable interface is used for the interface with the master processor, it may also be a simple memory means. As is clear from the above description, the present invention has the advantage of being able to speed up the interrupt response on the microprocessor side, as well as being able to transfer data from an external device with a simple configuration. Demonstrates excellent effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a block diagram showing another embodiment of the invention. 1... Master processor, 3... Decoder, 4, 4a,
4b...Slave processor, 5...Programmable
Verifical interface (PPI), 6... Input/output expansion unit, 7... Selector, 10...
Climb control circuit. Figure 1 Figure N Ship

Claims (1)

[Claims] 1. An interrupt control circuit that includes a processor that outputs an interrupt permission signal in response to an interrupt signal and executes interrupt response processing by referring to reference data from an external device, and supplies the interrupt signal and the reference data to the processor from the external device. a memory means for storing transfer data from an external device in a normal mode, and storing the reference data given from the external device before the generation of the interrupt signal in the interrupt mode; In the normal mode, the data read signal from the processor is input to the data read terminal of the memory means to transfer the transfer data to the data input of the processor, and in the interrupt mode, the interrupt enable signal is input to the data read terminal of the memory means. An interrupt control circuit comprising: a signal switching circuit input to a data read terminal to transfer the reference data to a data input of a processor.