JPH08241264A - Option device and information processor connected therewith - Google Patents

Abstract

PURPOSE: To automatically set addresses not to overlap one on another on address space when plural option devices are mounted, regarding the mechanism of automatically assigning the address on the address space of the bus of an information processor to the option device mounted on the bus. CONSTITUTION: This option device has a discrimination information holding means 1 holding values different from the other, an object bit designation means 2 designating a bit to be the check object of discrimination information and changing the bit after the check, a discrimination information check means 3 checking one bit of the discrimination information according to the instruction from a bus, performing a response if the value thereof is a preliminarily fixed value and performing a control so as to make a check a temporary stoppage state if not so, and a state control means 4 performing controls to a check so as to recover it from the temporary stoppage state to an operation state according to the instruction from the bus, transfer it from the temporary stoppage state to the stoppage state in which an instruction except a release instruction can not be accepted or return it to the operation state from the stoppage state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a mechanism for automatically assigning an address in a bus address space to an optional device (usually a card shape) mounted on a bus of an information processing device such as a personal computer or a workstation. Regarding

Address setting of an optional device has been done by a switch on the optional device in the past, but in recent years,
A method of setting a non-volatile memory such as an EEPROM and the like by writing the content by software (software setting method) has become common. Therefore, the user can set the setting information (usually, the settable range is limited) from the keyboard / display of the personal computer or the like through the address setting software attached to the option device.

However, address allocation when installing an optional device on a bus that does not have a physical identification means in each slot, such as the ISA bus often used in personal computers, is troublesome and error-prone. It is easy to cause trouble when installing the device.

[0004]

2. Description of the Related Art FIG. 3 shows an explanatory diagram of address allocation.
The optional device connected to the bus of the information processing device receives control instructions and operation mode designations from other devices (generally, the main body and processor) and performs predetermined operations.
It operates like returning a result. When another device gives a control instruction, it is generally performed by writing in a "control register" in the optional device. There are a plurality of "control registers", and a range in the address space of the bus can be assigned. The base address register holds the start address. It should be noted that the "control register" looks like a register when viewed from the bus, and is not necessarily configured by the register. For example, most of the "control register" is in memory, and by the control of the program by the microprocessor,
You may be dealing with a bus. Further, the contents of the control register may be common or different depending on the type of optional device.

Each control register can be addressed by the base address + α from the bus and read / write, or both. The optional device monitors the address of the bus and compares it with the contents of the base address register to grant access to the control register if it is within its range. Therefore, the addresses of a plurality of optional devices must be set so that they do not overlap, like A0, A1, ..., A4 in FIG.

The base address register itself is also one of the "control registers" and exists at an address within the allocation range. Therefore, when a value different from the original value is written in the base address register, the allocation of the address space is changed thereafter.

Therefore, when a new option device is added, it is necessary to write a set address that does not overlap the address setting of the existing option device into the base address register of the new option device.

[0008]

The optional device includes the following:
Normally, a predetermined value is written in the base address register as the default value of the address.
Therefore, since the same value is set at the time of purchase, this value easily matches the address of the existing optional device of the same type, and is the same when a plurality of optional devices of the same type are simultaneously installed. In this case, the contents of one or all base address registers must be reset to different values. At this time, it is not possible to give instructions to only one of the optional devices with multiple optional devices with the same address installed, so the optional devices can be removed and inserted, and the optional devices can be installed separately one by one. There is a problem that you have to do it.

An object of the present invention is to identify a plurality of option devices of the same type when they are mounted, and to automatically set addresses so that they do not overlap in the address space.

[0010]

The present invention has the following means in an option device which operates by being connected to a bus of an information processing device.

Identification information holding means consisting of a predetermined bit, which holds a value different from that of other optional devices. This identification information is unique to each optional device.

Target bit designation means for designating a bit to be checked in the identification information, and changing the designation of the target bit after checking. Normally, in the initial state, the target bit to be checked is the least significant digit (or most significant digit). Further, after the check, the designated object is changed to the one-bit upper (or lower) digit.

According to the instruction from the bus, the bit of the identification information designated by the target bit designating means is checked, and if it is a predetermined value, it responds to the bus, otherwise it does not respond, Identification information checking means for controlling so that the check instruction is not accepted thereafter so as to be in a temporary stop state.

The instruction from the bus in this case is usually given as an identification information check command. In response to an instruction from the bus, it returns from the suspended state to the operating state, or shifts from the suspended state to the stopped state that does not accept any instruction other than the release instruction, or controls to return from the stopped state to the operating state. means.

Normally, the instructions from the bus in this case are given as a return command, a stop command, and a release command, respectively. The information processing apparatus (the address setting mechanism thereof) of the present invention has means for performing the following operations on the option device having the above means.

Identification information check instruction means for instructing to check the identification information digit by digit via the bus. If there is a response to it, the device in the suspended state instructs to shift to the stopped state, and if there is no response,
Return / stop instruction means for instructing the device in the suspended state to return to the operating state.

Release instruction means for instructing to return from the stopped state to the operating state.

[0018]

The information processing device (the address setting mechanism thereof) normally sends the identification information check to the option device via the bus.
Give instructions for return, stop, and release in the form of commands.
In response to the identification information check instruction, each optional device checks the target bit at that time if it is in the operating state, and responds depending on whether it is a predetermined value (eg, “0”) Do not decide whether to be in a pause state. Originally, it does not react if it is in a suspended state or a stopped state.

In the initial state, the addresses of the same type of optional devices are the same, so if there are multiple options, the instruction is transmitted to the multiple optional devices. When all or some of a plurality of optional devices respond to the identification information check command, all of them may not respond.

When there is a response, the information processing apparatus (the address setting mechanism thereof) issues the stop command and then issues the identification information check command again. The bit of the identification information checked at this time is different from the previous bit. Also,
The optional device that did not respond the previous time has changed from the suspended state to the stopped state by the stop command, so the check itself is not performed and it does not respond.

If there is no response, the option device is either in a suspended state or originally in a suspended state because the target bit is not a predetermined value. When a return command is issued to these, those in the suspended state return to the operating state.

In this way, when the identification information check command is repeatedly issued to check all the bits, only one responding device can be set. Therefore,
If the address is set at this stage, it can be set only for the one optional device.

After this, a cancel command is issued to return the option device to which the address has not yet been set to the initial state (operating state), and by repeating the above operation, it is possible to set different addresses one by one. .

[0024]

1 is a block diagram of an embodiment of the present invention, showing an example in which the present invention is applied to one of optional equipment, a LAN card. The LAN cards 10a to 10c are mounted on the bus 30 of the information processing device, and other optional devices (not shown)
Similarly to the above, it operates according to an instruction from the main body device 20.

The LAN card 10 is constructed by connecting a microprocessor 11, a memory 12, an address buffer register 13, a data buffer register 14 and others to an internal bus. Most of the "control register" and other control registers are formed on the memory 12 and are operated programmatically by the control of the microprocessor 11. When the address data on the bus 30 changes, the contents are taken into the address buffer 13 and notified to the microprocessor 11 by an interrupt or the like. The microprocessor 11 checks the address and passes data between the bus 30 and the designated control register via the data buffer 14 if it has designated one of its control registers.

A part of the memory is made of a non-volatile element such as an EEPROM and holds the base address register 5 and the identification information holding register 1. The current LAN card can be given a MAC global address (hereinafter referred to as "MAC address"), which is the only one in the world and has a hexadecimal 12-digit address. This is defined as the IEEE (American Electrical and Electronic Engineers Boundary) standard, and manufacturers can obtain a certain range of addresses by applying and registering with IEEE, and uniquely assign it to their products. . This address is for distinction in the world of LAN, and the same value of M
No other LAN card has an AC address (which is quite different from the address on the bus). In the present embodiment, this is used as identification information to distinguish each optional device and determine the address on the bus.

Besides, a target bit designation register 2 for designating a bit of the identification information holding register 1, identification information check means (program) 3, state control means (program)
4, special command register 6, and other control register group 7. Other control register groups 7 not related to the present invention will not be mentioned.

The main unit 20 is composed of a processor 21, a memory 22, etc., and operates an address setting mechanism program having an identification information check instruction means 31, a return / stop instruction means 32, and a release instruction means 33.

A plurality of cards 10a having the same address set,
When there are 10b and 10c, when the address is specified on the bus 30, a plurality of cards 10a, 10b and 10c simultaneously respond. Therefore, even if the internal information is read as it is, it cannot be read normally. Also, different contents cannot be written in each.

The cards 10a, 10b, 10c of this embodiment are the bus 30
It has the function of decoding and executing the special command given from the processor 21 via. The special command is given in the form of an identification information check command, a return command, a stop command, and a release command. These commands
21 designates by writing in a specified register (special command register shown in FIG. 3) in the address space. This is written in the special command register 6 on the memory 12 via the address buffer 13 and the data buffer 14.

The operation of the embodiment of the present invention will be described below with reference to the operation explanation flow charts of FIG. 1 and FIG.
Every time the main unit 20 gives an identification information check command via the bus 30 (P1, S1), each card 10a,
10b and 10c are M designated by the target bit designation register 2
Look at the bit (target bit: least significant bit in the initial state) of the AC address (S2), and if it is '0', respond (S3),
If it is "1", it does not respond and enters a pause state (S4).
On the contrary, this correspondence may be such that if it is "1", it responds, and if it is "0", it does not respond.

After that, the contents of the target bit designation register 2 are incremented (S5) and the target bit is changed to the next (upper) bit. The target bit change command may be provided and the target bit may be changed according to the instruction.

If any of the identification information check commands responds (there may be a plurality, but it cannot be distinguished at this stage), the main body device 20 issues a stop command (P3). When this command is issued, the card in the suspended state (card that did not respond) is in the stopped state (S7, S10),
After that, it responds only to the release command. If the target bit of all the cards is "1", no card responds, and the main body device 20 detects the timeout or the like (P2). At this time, the main body device 20 issues a return command (P4). By this command, the card in the suspended state is activated again (S7, S8), and responds to the identification information check command.

When the identification information check command is given again (P1), the card checks the bit one higher than the MAC address as the target bit. Hereinafter, the same operation as described above is performed.

When the above-mentioned processing is repeated for the number of bits of the MAC address, only one card is in operation at the end. In this state, the card (the last one left after processing all the bits) can be put into normal bus operation. Therefore, the base address register 5 of this card is written (P6), and the setting is changed to an address different from that of other cards that have stopped responding. with this,
This card was separated from other cards.

When a cancel command is issued to another card (card whose address has not been changed) (P7), they return to the initial state. Again for those cards first
By performing the same operation from (P1), unique addresses can be given one after another.

Specific examples of these processes will be described below.
In this example, the MAC addresses of the three cards are as follows. Card 10a MAC address (bit row) 00 ... 101110110101 Card 10b MAC address (bit row) 00. Issue identification information check command. (In the initial state, the target bit is the least significant bit.) When receiving the identification information check command, each card checks the least significant bit. ⇒Because all the cards are '1', they are in a suspended state,
None respond. 2. Timeout is detected because there is no response. Issue a return command.

⇒ Each card returns to the operating state. 3. Issue identification information check command. (Each card has already changed the target bit to 1 bit higher.) ⇒ Each card checks the second bit from the lower bit.

=> All cards are '0', so respond. 4. Since there was a response, a stop command was issued. (⇒ There is no card in a suspended state, so there is no particular change.) Issue identification information check command.

⇒ Each card checks the third bit from the lower order. () ⇒ Card 10a is "1", so it is suspended. => Cards 10b and 10c respond because they are '0'. 6. Since there is a response, issue a stop command.

⇒ The card 10a in the suspended state is in the suspended state. 7. Issue identification information check command. ⇒ All (cards 10b, 10c) are '1', so they are in a suspended state and do not respond. () (Card 10a is already in a stopped state, so it does not respond even if it is '0') 8. Detects a timeout and issues a return command.

⇒ The cards 10b and 10c return to the operating state. (Because the card 10a is in the stopped state, it does not enter the operating state at this time.) Issue identification information check command.

⇒ Since the card 10c is "1", it is temporarily stopped. Ten. Since there is a response (card 10b), issue a stop command. ⇒ Card 10c is stopped.

Thereafter, the same operation is repeated up to the most significant bit so that only one card (card 10b) is in the operating state. 11. At this time, if the base address register is rewritten by standard operation of the bus, the allocation position in the address space of the operable card becomes different.

The address value should not overlap with the address area of an existing card within the range allowed for the card (generally, due to hardware and software restrictions). 12. Then, it is returned to the initial state by the release command.

If the same operation is performed thereafter, the card 10
c can be separated from the card 10a. (Card 10
b is excluded because it already has a different address. Although the MAC address is used as the identification information in the LAN card of the present embodiment, the serial number such as the serial number may be written as the identification information in the type of card for which such information cannot be obtained. . In this case, if the identification information is set to the same location in the same format (including LAN cards) regardless of the card type and the address setting location is the same, the configuration of the address setting program is easy. Can be

[0047]

As described above, according to the present invention,
Even if there are a plurality of optional devices of the same type having the same address setting on the bus, they can be automatically assigned to different address spaces. Therefore, the address setting can be automatically performed without pointing out the optional device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

[Fig. 2] Operation explanation flowchart

[Figure 3] Address allocation explanatory diagram

[Explanation of symbols]

1 identification information holding means 2 target bit designating means 3 identification information checking means 4 state control means 5 base address register 6 special command register 7 other control register group 10a, 10b, 10c option device (LAN card) 11 microprocessor 12 memory 13 Address buffer register 14 Data buffer register 20 Main unit 21 Processor 22 Memory 31 Identification information check means 32 Return / stop instruction means 33 Release instruction means

Claims (2)

[Claims] 1. An optional device which is connected to a bus of an information processing device to operate and has the following means. An identification information holding unit having a predetermined bit, which holds a value different from those of other optional devices. Target bit designation means for designating a bit to be checked for identification information, and changing the designation of the target bit after the check. In response to the instruction from the bus, the bit of the identification information designated by the target bit designating means is checked, and if the result is a predetermined value, it responds to the bus, otherwise it does not respond and Identification information checking means for controlling so that a check instruction is not accepted thereafter so as to be in a suspended state. In response to an instruction from the bus, it returns from the suspended state to the operating state, or shifts from the suspended state to the stopped state that does not accept any instruction other than the release instruction, or controls to return from the stopped state to the operating state. means. 2. An information processing apparatus having means for performing the following operations with respect to the option device according to claim 1. Means for instructing to check 1 bit of identification information. Whether or not there is a response to the instruction, if there is a response, the device in the suspended state is instructed to shift to the suspended state, and if there is no response, the device in the suspended state returns to the operating state. Means to instruct you to do. A means to instruct to return from the stopped state to the operating state.