KR20010018243A - Register mapping method for micro processor - Google Patents

Abstract

PURPOSE: A method for mapping register of a micro processor is provided to enhance of an operation speed by minimizing the difference of capacitance values in each bit of a data bus in accordance with identifying the number of registers connected to each bit of all internal data buses when a register of micro processor is mapped, thereby adapting design area of an actuator and power consumption suitably. CONSTITUTION: A register(110¯125) outputs data through a system bus(100) and a 32 bits data bus(D<31:0>). The register(110, 111, 120, 121, 122) consist of 32 bits register inputting and outputting 32 bits data by an input/output unit controlled by a micro processor through data buses(D<31:0>). The register(112)(113)(115)(116)(117)(118) consist of 16 bits register adding two registers(112,113) (115,116) (117,118) for inputting/outputting data through data buses(D<31:0>). The 16 bits register outputs each 16 bits data to the system bus(100) through input and output units(130)(131) enabled by read and write enable signals(RDEN1, RDEN2) (WDEN1, WDEN2) from the micro processor and data buses(D<15:0>)(D <31:16>). In addition, the 16 bits register receives and outputs 16 bits data of the system bus(100). The register(114)(119)(123)(124) consist of 8 bits register adding four registers(114)(119)(123)(124) for inputting/outputting data through data buses(D<31:0>). The 8 bits register receives and outputs each 8 bits data to the system bus(100) through the input and output units enabled by data buses(D<7:0>)(D <D<15:8>)(D<23:16>)(D<31:24>) and the micro processor.

Description

Register mapping method of microprocessor {REGISTER MAPPING METHOD FOR MICRO PROCESSOR}

The present invention relates to a register mapping method of a microprocessor, and more particularly, to a method of mapping a register of a microprocessor such that the load capacitance value of an internal data bus is the same for all data buses in mapping registers of the microprocessor.

Register mapping of a conventional 32-bit microprocessor is performed by a 32-bit system bus 10 and a data bus D <31: 0> (D <15: 0>) (D <7: 0>) as shown in FIG. The first to the fifteenth register (20 to 35) for inputting and outputting data through the ().

The registers 22, 23, 25, 26, 27, and 28 are read and write enable signals RDEN1 to RDEN6 of a microprocessor (not shown), respectively, as shown in FIG. The 16-bit data is output to the system bus 10 through the data bus D <15: 0> by the input / output units 40 to 45 enabled by the WDEN1 to WDEN6, or on the system bus 10. Each consists of 16-bit registers that receive and store 16-bit data.

The registers 20, 21, 30, 31, and 32 respectively input and output 32-bit data through the data bus D <31: 0> by the input / output unit under the control of the microprocessor. Each of the registers 24, 29, 33, and 34 is composed of 32 bit registers. The registers 24, 29, 33, and 34 are each composed of 8 bits of data through the data bus D <7: 0>. Each of the 8-bit registers for inputting and outputting are described in detail.

In general, since the register bits of the microprocessors have different register bits according to their functions, the register bit size of the 32-bit microprocessor is composed of a maximum of 32 bits and a minimum of 8 bits.

Therefore, register mapping sets the address and data bus of a specific register. In general, the data bus is used by designating as many bits as necessary, starting from the lower bits.

That is, the 32-bit register uses the lower 0 bits and the upper 31 bits of the data bus, and the 16-bit register uses the 0 to 15 bits of the data bus, and the 8-bit register uses 0 of the data bus. Bits to 7 bits are used.

For example, when 16-bit data is to be stored in the register 22, the input / output unit 40 is enabled by the write enable signal RDEN, and the 16-bit data of the system bus 10 is converted into the data bus D. FIG. &Lt; 15: 0 &gt;) in the register 22.

In addition, other 16-bit registers 23, 25, 26, 27, and 28 also input 16-bit data of the system bus 10 through the data bus D <15: 0> in the same manner as described above. Receive and save.

In the case of reading 16-bit data from the 16-bit registers 22, 23, 25, 26, 27, and 28, the input / output unit 40 to 45 by the read enable signal RDEN. ) Is enabled and outputs the stored 16-bit data to the system bus 10 via the data bus D <15: 0>.

Here, since the number of registers connected to each bit in the data bus is different, modeling each register according to the number of bits of the register connected to the data bus, the capacitance value of each bit of the data bus according to the number of connected registers The smaller the connected register is, the larger it is.

As described above, in the prior art, the smaller the number of registers connected to each bit of the data bus, the larger the capacitance value, and the larger the design area and power consumption of the driver, and the more the actual capacitance value is achieved by the bits of the data bus. As the operating speed is determined, there is a problem that the overall speed is lowered.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems. In the mapping of the registers of the microprocessor, the method of mapping the registers of the microprocessor such that the load capacitance values of the internal data buses are the same for all data buses. The purpose is to provide.

1 is a block diagram illustrating register mapping of a conventional 32-bit microprocessor.

FIG. 2 is a circuit diagram illustrating a configuration of third and fourth registers in FIG. 1.

3 is a block diagram showing register mapping of a 32-bit microprocessor to which the present invention is applied;

FIG. 4 is a circuit diagram illustrating a configuration of third and fourth registers in FIG. 3.

*** Description of the symbols for the main parts of the drawings ***

100: system bus 110-125: register

130,132: I / O part

The present invention for achieving the above object is a combination of two or more registers to each other to have the same bit and the plurality of registers in the multi-bit microprocessor to map the registers having a different number of bits each through a multi-bit data bus It is characterized in that the data input and output.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

FIG. 3 is a block diagram showing register mapping of a 32-bit microprocessor to which the present invention is applied. As shown in FIG. 3, data is inputted and outputted through a system bus 100 and a 32-bit data bus D <31: 0>. And registers 110 to 125, and the registers 110, 111, 120, 121, and 122 are respectively controlled by a data bus (D &lt; 31) by an input / output unit controlled by a microprocessor (not shown). It consists of 32-bit registers that input and output 32-bit data through: 0>).

In addition, two registers 112, 113, 115, 116, 117, and 118 are provided for inputting and outputting data through the data bus D <31: 0>, as shown in FIG. Input and output units 130 and 131 enabled by the read and write enable signals RDEN1 and RDEN2 (WDEN1 and WDEN2) from the microprocessor after the registers 112 and 113 and 115 and 116 and 117 and 118 are combined. Outputting 16-bit data to the system bus 100 or receiving and storing 16-bit data of the system bus 100 through a data bus D <15: 0> (D <31:16>). Each of the four registers 114 and 119 is configured as a 16-bit register, and registers 114, 119, 123, and 124 are used to input and output data through the data bus D <31: 0>. (123) and (124) are combined, respectively, to the data bus (D <7: 0>) (D <15: 8>) (D <23:16>) (D <31:24>) and the microprocessor, respectively. Enabled by Configuration, each with an 8-bit register for inputting and outputting eight-bit data through input and output units, and a description of the operation procedure according to the present invention constructed as described immediately above in detail.

First, for each non-32-bit register, it connects to each other to input and output data to the system bus 100 via the data bus (D <31: 0>) within the 32-bit range so that it behaves like a 32-bit register. do.

That is, in the case of the 16-bit registers 112, 113, 115, 116, 117, and 118, two of them are put together and connected through the data bus (D <31: 0>) to connect each 16-bit data. In the case of the 8-bit registers 114, 119, 123, and 124, four are combined and connected through the data bus D <31: 0> to input and output data.

In this case, when 16-bit data is written to the 16-bit registers 112 and 113, the input / output units 130 and 131 are enabled by the write enable signals WDEN1 and WDEN2 of the microprocessor. 16-bit data of 100 is inputted through a data bus (D <15: 0>) (D <31:16>) and stored.

When the data stored in the 16-bit registers 112 and 113 is to be read, the input / output units 130 and 131 are enabled by the read enable signals RDEN1 and RDEN2 to store the 16-bit data. Data is output to the system bus 100 via a data bus D <15: 0> (D <31:16>).

In the case of writing 8-bit data, the data bus D <7: 0> (D <15: 8>) (D <23:16>) ( D <31:24>) stores 8-bit data in the respective 8-bit registers 114, 119, 123, and 124, and reads the 8-bit register 114 by a read enable signal when reading. The 8-bit data stored in 119, 123, and 124 is respectively converted into a data bus (D <7: 0>) (D <15: 8>) (D <23:16>) (D <31:24>). Output to the system bus 100 through.

Here, the microprocessor combines a plurality of registers to input and output data using a data bus (D <31: 0>) like a 32-bit register, but applies a separate read and write enable signal to each input / output unit. By enabling the control, data is read / written to each register.

As described in detail above, the present invention minimizes the difference in capacitance value of each bit of the data bus by matching the number of registers connected to each bit of all internal data buses when mapping the registers of the microprocessor. It has the effect of improving overall operating speed by optimizing design area and power consumption.

Claims (1)

When mapping a register having a different number of bits in a multi-bit microprocessor, two or more registers are combined with each other to have the same bit as each of the plurality of bit registers to input and output the respective data through the multi-bit data bus. How a processor maps registers.