JPH08179965A - Event detection circuit - Google Patents

Abstract

PURPOSE: To provide a superior function as an event detecting function and to provide a high-degree event combination with a low cost and at high speed by detecting the occurrence of prescribed combination of input information by combining information outputted in parallel from an information storage means. CONSTITUTION: Each set data of designated condition to detect each input intended event is stored corresponding to each of the addresses 21a-21d of a detection event designation register 21. Comparators 20a-20d compare designation data from the corresponding addresses of the detection event designation register 21 with an address and data inputted from a bus 9 and executed by a target microcomputer, and detect a prescribed event by detecting coincidence between the data. Each shift registers 23a-23d performs one-bit shift setting the corresponding comparison output of the comparators 20a-20d as input data, and each data is outputted to a combinational logic circuit 24 for detection simultaneously and in parallel as parallel data, and the combination of set events is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an event detection circuit used in a debug device for debugging hardware and software of a microprocessor application system or the like.

[0002]

2. Description of the Related Art When debugging the processing operation of a microprocessor application system, it is necessary to grasp the actual operation phenomenon in order to study the cause and countermeasure for the operation different from the operation intended at the time of designing the system. . For this purpose, a function of monitoring the operation of the microprocessor and stopping the target processing under a specific condition is required in order to grasp the operation state at the time of occurrence of the problematic phenomenon.
In this case, the specified specific condition is expressed as an event, and the debug device has an event detection function for detecting the event.

FIG. 11 is a schematic block diagram of an event detection circuit having a conventional sequential event detection function. In FIG. 11, the comparator unit 100 is composed of comparators 100a, 100b, 100c, 100d, and comparators 100a, 100b, 100c, 1
One input of 00d is a microcomputer application system to be debugged (hereinafter referred to as a target system)
Is connected to a bus 101 of a microcomputer to be debugged (hereinafter referred to as a target microcomputer).

Further, the other inputs of the comparators 100a to 100d are connected to the detection event designation register 102 which stores the event to be detected, and each event to be detected is stored in each address of the register 102. , The comparators 100a to 10
0d compares the status data stored in the address with the status data (address, information data, etc.) input from the bus 101, and detects a match with the data.

Here, as an example, the comparator 10 is used.
The other input of 0a is the address 1 of the register 102.
The event state data stored in the comparator 100b is stored in the other input of the comparator 100b, and the event state data stored in the address 2 of the register 102 is stored in the other input of the comparator 100b.
The event state data stored at address 3 of the register is input to the other input of the comparator 100d, and the event state data stored at address 4 of the register 102 is input. Further, the outputs of the comparators 100a to 100d are connected to an event detection sequencer 103 for forming and designating a combination of sequences.

In the above configuration, the event detection sequencer 103 is set to the state S1 as an initial state, and when the coincidence detection signal is input from the comparator 100a to the event detection sequencer 103, the event detection sequencer 103 The state S1 transits to the state S2. Similarly, when the coincidence detection signal is input from the comparator 100b to the event detection sequencer 103, the event detection sequencer 103 transits from state S2 to state S3, and from state S3, the comparator 1
The coincidence detection signal 00d causes a transition to state S4. When the internal state of the event detection sequencer 103 reaches the state S4, the event detection sequencer 103 outputs an event detection signal.

The event detection sequencer 103 is also provided.
When the match detection signal is input from the comparator 102d to the event detection sequencer 103 in the state S2, the event detection sequencer 103 transits from the state S2 to the state S4 and outputs the event detection signal.

Thus, the comparators 100a-10a
0d, the status data stored in each address of the detection event designation register 102 and the bus 101
By comparing with the data of the state (address, information data, etc.) input from the target microcomputer, the bus access of the target microcomputer can be performed by the detection event designation register 102.
The event detection sequencer 10 indicates that processing of a series of stored contents such as address 1 to address 2 and address 4 or address 1 to address 4 has occurred.
3 is detected.

[0009]

However, as described above, since the combination of sequences is conventionally designated by the configuration of the event detection sequencer 103, the configuration of the event detection sequencer 103 is generally fixed and the comparator unit 100 is operated. The intended sequential event detection was specified by setting the event specification of in accordance with the required sequence. For this reason, the event management becomes complicated, the hardware and software configurations become complicated, and the increase in the number of stages of sequences to be detected in the event detection sequencer 103 requires an increase in the circuit of the event detection sequencer 103. Therefore, only the sequence of about 6 steps was realized.

The present invention has been made to solve the above problems, and among the functions of a debugging device that supports debugging of a microprocessor application system,
(EN) A means for enhancing an event detection function used for breakpoint detection or the like and realizing an advanced event combination at low cost and at high speed.

[0011]

According to the present invention, input information is stored in time series, and the stored time series information is simultaneously output in parallel, and the information storage means outputs the information in parallel. An event detection circuit for detecting a predetermined event is provided, which is provided with a combination detection means for detecting the occurrence of a predetermined combination of the input information by combining the generated information.

The invention according to claim 2 of the present application is characterized in that the information storage means according to claim 1 comprises at least one shift register.

In the invention according to claim 3 of the present application, the combination detecting means according to claim 1 and claim 2 has a PLA structure in which the input information is input to the AND array section. Is characterized by.

According to a fourth aspect of the present invention, there is provided bus state detection means for monitoring a bus state of a microprocessor and outputting a predetermined detection signal when a designated state is detected, and the bus state detection means. A signal output means for outputting a predetermined signal when the detection signal is output from the bus state detection means, and a predetermined signal from the signal output means for storing the output signal from the bus state detection means in time series. ,
By combining the storage means having the function of simultaneously outputting the stored time-series signal information in parallel and the signal information output in parallel from the storage means, and detecting the occurrence of a predetermined combination of the signal information. The present invention provides an event detection circuit in a debug device for debugging a microprocessor application system or the like, which comprises a combination detection means for detecting a specific event in the microprocessor.

In the invention according to claim 5 of the present application, the storage means according to claim 4 comprises a plurality of shift registers.

In the invention according to claim 6 of the present application, the combination detecting means according to claims 4 and 5 has a PLA structure in which the signal information is input to the AND array section. Is characterized by.

The invention according to claim 7 of the present application monitors the bus state of the microprocessor, compares the bus state with a designated state, and when a match occurs, outputs a predetermined signal. A plurality of comparator circuits to output, a comparator pulse output circuit that outputs a pulse signal when the predetermined signal is output from any one of the comparator circuits, and shifted by the pulse signal from the comparator pulse output circuit, A plurality of shift registers having a function of storing the output states from the comparator circuits and outputting the stored information in parallel at the same time, and a combination of the signal information output from the shift registers in parallel. By detecting the occurrence of a predetermined combination of the signal information, a specific bus state in the microprocessor is detected. And a combinational logic circuit output,
An event detection circuit in a debug device for debugging a microprocessor application system or the like.

The invention according to claim 8 of the present application is characterized in that the combinational logic circuit according to claim 7 has a PLA structure in which the signal information is input to an AND array section.

[0019]

In the event detection circuit according to claim 1, the information storage means stores the input information in time series, and outputs the stored time series information simultaneously in parallel. The combination detection means combines the information output in parallel from the information storage means to detect the occurrence of a predetermined combination of the input information.

In the event detection circuit according to claim 2 of the invention, the information storage means according to claim 1 comprises at least one shift register.

In the event detection circuit according to claim 3 of the invention, the combination detection means according to claims 1 and 2 has a PLA structure in which the input information is input to the AND array section. Eggplant

According to another aspect of the present invention, in the event detecting circuit, the bus state detecting means monitors the bus state of the microprocessor and outputs a predetermined detection signal when the designated state is detected. The signal output means outputs a predetermined signal when the detection signal is output from the bus state detection means, and the storage means outputs the output signal from the bus state detection means according to the predetermined signal from the signal output means. Along with storing in time series, the stored time series signal information is simultaneously output in parallel, and the combination detecting means combines the signal information output in parallel from the storage means to obtain a predetermined combination of the signal information. By detecting the occurrence, a specific event in the microprocessor is detected.

In the event detection circuit according to claim 5 of the invention, the storage means according to claim 4 is:
It is composed of a plurality of shift registers.

In the event detection circuit according to claim 6, the combination detection means according to claims 4 and 5 has a PLA structure in which the signal information is input to the AND array section. Eggplant

According to another aspect of the event detection circuit of the present invention, each comparator circuit monitors the bus state of the microprocessor and compares the bus state with a designated state. Outputs a predetermined signal and outputs a pulse signal when the comparator pulse output circuit outputs the predetermined signal from any of the comparator circuits, and each shift register outputs a pulse from the comparator pulse output circuit. Shifted by a signal, store the output states from the comparator circuits, respectively, output the stored information in parallel at the same time, and the combinational logic circuit outputs the signal information output in parallel from the shift registers. In combination, the occurrence of a predetermined combination of the signal information is detected to detect a particular bar in the microprocessor. State to detect.

In the event detection circuit according to claim 8 of the present invention, the combinational logic circuit according to claim 7 uses the signal information as an input to the AND array section.
Form A structure.

[0027]

The present invention will now be described in detail with reference to the embodiments shown in the drawings. Example 1. FIG. 1 is a schematic block diagram showing an example of a debug device using the event detection circuit according to the first embodiment of the present invention, which has a function of capturing and recording bus information of a microprocessor and debugs a microprocessor application system or the like. FIG. 1 is a diagram. First, an outline of a debug device using the event detection circuit of the first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, a debug device 1 generally uses a microcomputer of the same type as the target microcomputer or a microcomputer to which a debugging function is added, and an emulation microcomputer 2 for realizing the function of the target microcomputer in the debug device 1. Emulation microcomputer control circuit 3 for controlling the operation of the emulation microcomputer 2 and switching between the operation in the target system and the operation in the debug device 1.
And event detection circuits 4a and 4b that monitor the operation of the target microcomputer and detect the occurrence of a specified condition that is the address executed by the target microcomputer or the data accessed.
And a break circuit 5 having a function of controlling the interrupt control function of the emulation microcomputer control circuit based on the condition detected by the event detection circuit 4a.

The debug device 1 further includes a trace memory 6 for recording the bus operation of the target microcomputer.
And a trace function for recording the bus operation of the target microcomputer (emulation microcomputer in the debugger), controlling the address in the trace memory 6 and recording start or end operation according to the conditions set by the event detection circuit 4b. And a trace control circuit 7 for controlling the emulator, and an emulator control MP which is a bus used for performing settings inside the debugger and data processing for executing the debugger commands by controlling the inside of the debug device 1.
And a U-bus 8.

Further, the emulation microcomputer 2,
The event detection circuits 4a and 4b and the trace memory 6 are
The event detection circuits 4a and 4b, the break circuit 5, the trace memory 6 and the trace control circuit 7 are connected to the target system by a bus 9 including an address bus, a data bus, a control bus, etc. Further, the break circuit 5 is connected to the emulation microcomputer control circuit 3 via 8, and the break circuit 5 is connected to the emulation microcomputer control circuit 3 separately. The event detection circuit 4a is provided in the break circuit 5, and the event detection circuit 4b is provided in the trace control circuit 7.

In the above-described configuration, the debug operation of the debug apparatus 1 is known, and the operation of controlling and observing the operation of the target microcomputer will be briefly described here. First, the operation of controlling the operation of the target microcomputer in the debug device 1 shown in FIG. 1 will be described. The main function of the target microcomputer operation control is to detect the conditions specified during execution of the target program, which is the software that the target microcomputer executes on the target system. When the conditions are detected, the target program is executed to the target microcomputer. Is to interrupt.

FIG. 2 is a flow chart showing the operation for controlling the operation of the target microcomputer by the debug device 1 in FIG. 1. The operation for controlling the operation of the target microcomputer by the debug device 1 will be described with reference to the flow chart of FIG. . In FIG. 2, first, in step S1, the emulation microcomputer control circuit 3 inputs data of a condition to be detected to the event detection circuit 4a via the emulator control MPU bus 8 to set the condition, and in step S2. The event detection circuit 4a detects the specified condition by comparing the specified condition set with the address and data executed by the target microcomputer input from the bus 9.

Next, at step S3, the event detection circuit 4a
If the above specified condition is detected (YES), step S
In step 4, the event detection circuit 4a outputs a signal indicating that the specified condition is detected to the break circuit 5, and in step S5, the break circuit 5 receives the signal from the event detection circuit 4a and controls the emulation microcomputer. Circuit 3
On the other hand, for example, a break request signal for operating a predetermined interrupt control function such as generating an interrupt in the emulation microcomputer 2 is output, and step S6
Then, the emulation microcomputer control circuit 3 causes the emulation microcomputer 2 to perform a predetermined interrupt operation such as interrupting the execution of the target program in the target system, and this flow ends.

In step S3, the event detection circuit 4
If a does not detect the specified condition (NO), the process returns to step S2, and the event detection circuit 4a performs the detection operation until the specified condition is detected. Since the emulation microcomputer control circuit 3 can input the data of the condition to be detected to the event detection circuit 4a via the emulator control MPU bus 8 to set the condition, the emulation microcomputer control circuit 3 detects the event detection circuit 4a at any time. The desired condition is changed and the setting is performed.

Next, the operation of observing the operation of the target microcomputer in the debug device 1 shown in FIG. 1 will be described. The main function of the target microcomputer operation observation is the trace function that records the bus cycle by the software executed by the target microcomputer. FIG.
3 is a flowchart showing the operation of observing the operation of the target microcomputer by the debug device 1 in FIG. 1, and the operation of observing the operation of the target microcomputer by the debug device 1 will be described using the flowchart of FIG.

In FIG. 3, first, in step S10, the emulation microcomputer control circuit 3 sends data specifying a range to be recorded in the bus operation of the target microcomputer to the event detection circuit 4b via the emulator control MPU bus 8. The condition for inputting and setting the range, that is, the address data of the range to be detected in the bus cycle of the target microcomputer is specified, and in step S11, the event detecting circuit 4b receives the condition specifying condition and the bus 9 from the bus 9. The address data in the bus cycle of the target microcomputer is compared to detect the specified condition.

Next, at step S12, the event detection circuit 4
When b specifies the specified condition, that is, the condition to start recording (YES), the event detection circuit 4b outputs a signal indicating that the condition to start recording is detected to the trace control circuit 7 in step S13. And step S1
At 4, the trace control circuit 7 receives the signal from the event detection circuit 4b, controls the address of the trace memory 6 and outputs a signal to start recording to the trace memory 6, and proceeds to step S15. If the event detection circuit 4b does not detect the recording start condition in step S12 (NO), the process returns to step S11, and the event detection circuit 4b performs the detection operation until the specified condition is detected.

In step S15, the trace memory 6
Receives the recording start signal from the trace control circuit 7, and continues recording the bus operation of the target microcomputer input from the bus 9 at the designated address. Next, in step S16, the event detection circuit 4b detects the specified condition, that is, the condition for ending the recording, and the step S1
When the event detection circuit 4b detects the condition for ending the recording in 7 (YES), the event detection circuit 4b outputs a signal indicating that the condition for ending the recording is detected to the trace control circuit 7 in step S18. And step S
Proceed to 19.

In step S19, the trace control circuit 7
In response to the above signal from the event detection circuit 4b, a signal for ending the recording is output to the trace memory 6, and the trace memory 6 ends the recording of the bus operation of the target microcomputer input from the bus 9 in step S20. This flow ends. When the event detection circuit 4b does not detect the condition for ending the recording in step S17 (NO), the process returns to step S16, and the event detection circuit 4b continues the operation until the specified condition for ending the recording is detected. Perform detection operation.

Next, FIG. 4 shows a first embodiment of the event detection circuit of the present invention for use in the event detection circuits 4a and 4b provided in the break circuit 5 and the trace control circuit 7 shown in FIG. FIG. 2 is a block diagram of the sequential event detection circuit shown in FIG.
The event detection circuit according to the first embodiment of the present invention will be described with reference to FIG. In addition,
4, the same components as those shown in the schematic block diagram of the debug device in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

In FIG. 4, event detection circuits 4a, 4
Reference numeral b is a comparator section 20 and a detection event designation register 21 which form a bus state detecting means, a comparator pulse generating circuit 22 which forms a signal outputting means, an event shift register 23 which forms an information detecting means and a storing means, and an event which forms a combination detecting means. It is composed of a detection combinational logic circuit 24. The comparator unit 20 includes comparators 20a and 2a.
0b, 20c, 20d, and the comparator 20a,
One input of each of 20b, 20c and 20d is connected to the bus 9.

Further, the detected event designation register 21 in which setting data of respective designated conditions for detecting each intended event is stored is provided in the comparator 20a.
To 20d are connected to the other inputs respectively, the setting data under the specified condition for detecting each intended event is stored in each address of the register 21, and the comparators 20a to 20d store in that address. The set data thus obtained is compared with the data in the state (address, information data, etc.) input from the bus 9 to detect a match with the data.

Here, as an example, the comparator 20 is used.
The other input of a is the address 21a of the register 21.
The setting data for detecting the intended event, which is stored in, is input to the other input of the comparator 20b for detecting the other intended event stored in the address 21b of the register 21. The setting data is input. Further, the other input of the comparator 20c receives the setting data stored in the address 21c of the register 21 for detecting another intended event, and the other input of the comparator 20d receives the register. The setting data for detecting another intended event stored at the address 21c of 21 is input.

The comparators 20a to 20d are also provided.
Outputs multiple shift registers, here 4 as an example.
The output of the comparator 20a is connected to the event shift register 23 composed of two shift registers 23a, 23b, 23c and 23d.
a, the output of the comparator 20b is the shift register 23
b, the output of the comparator 20c is the shift register 23
c, the output of the comparator 20d is the shift register 23
each of the shift registers 23a to 23d of the event shift register 23 is connected to
It is stored as internal information of 23d.

Further, the outputs of the comparators 20a to 20d are also connected to a comparator pulse generating circuit 22 which outputs a pulse signal when detecting the respective coincidence detection signals output from the comparators 20a to 20d. The outputs of the comparator pulse generating circuit 22 are connected to the shift registers 23a to 23d, respectively, and the pulse signals output from the comparator pulse generating circuit 22 form shift clock signals of the shift registers 23a to 23d.

The outputs of the shift registers 23a-23d are connected to the event detection combinational logic circuit 24. The event detection combination logic circuit 24 has a PLA structure and can detect a target event combination by selecting a necessary combination. The respective data stored in the shift registers 23a to 23d are simultaneously output as parallel data to the event detection combinational logic circuit 24.

When the data bits of these shift registers are viewed in a matrix, the matrix includes all combinations of AND, OR, and sequential relating to the occurrence of a plurality of designated events, and the combination for event detection is selected from the matrix. PLA of logic circuit 24
Depending on the structure, a desired combination of events is detected by selecting a necessary combination, and when the combination is detected, the detection signal is output to the break circuit 5 shown in FIG.

In the above configuration, since the events detected by the comparators 20a to 20d are equivalent, the event setting to each of the comparators 20a to 20d is set without paying attention to the intended combination of events. A combinational logic circuit 24 for event detection
The PLA plane in the PLA structure used for
Since it is possible to adopt a configuration in which the logical structure of the base switch matrix is changed, the combination of events to be detected can be changed at any time by software. In the present embodiment, the emulation microcomputer control circuit 3 causes the emulator to change. Through the control MPU bus 8, the combination of events detected by the event detection combination logic circuit 24 is changed at any time.

Next, the operation of detecting a combination of events in the event detection circuit of the present invention shown in FIG. 4 will be described with reference to the flowchart of FIG. In FIG. 5, first, in step S30, each set data of each specified condition for detecting each intended event, which is input from the emulation microcomputer control circuit 3 via the emulator control MPU bus 8, is the detected event designation. It is stored corresponding to each address 21a to 21d of the register 21, and in step S31, each comparator 20a to 20d is stored.
Respectively correspond to the detection event designation registers 21
Setting data from this address is compared with the address and data executed by the target microcomputer input from the bus 9, and the coincidence with the data is detected to detect a predetermined event.

Next, in step S32, when at least one of the comparators 20a to 20d detects a predetermined event and outputs an event detection signal (YE
S), the comparator pulse generation circuit 2 in step S33
2 detects that the outputs of the comparators 20a to 20d have changed, outputs the detection pulse signal to the shift registers 23a to 23d of the event shift register 23 as shift clock signals, and proceeds to step S34. In step S32, the comparators 20a-2
When all of 0d do not detect the predetermined event (NO), the process returns to step S31.

In step S34, each shift register 23a
23d are 1 bit shifted by using the comparison output of the corresponding comparators 20a to 20d as input data, and in step S35, the data of the shift registers 23a to 23d in the event shift register 23 are detected in parallel as parallel data at the same time. Combinational logic circuit 2
4 and the process proceeds to step S36.

The event detection combination logic circuit 24 detects the combination of the set events in step S36, and if the event combination set in step S37 is detected (YES), the combination is set in step S38. The event combination detection signal indicating that the event combination has been detected is output to the break circuit 5 in FIG. 1, and this flow ends. If the event detection combination logic circuit 24 does not detect the set event combination in step S37 (NO), the process returns to step S30 to perform the processing of step S30 and thereafter.

Next, FIG. 6 shows the first embodiment of the present invention shown in FIG.
FIG. 7 is a block diagram showing a sequential event detection circuit having a configuration in which the number of detected events is 4 and the number of sequential stages is 6 in the event detection circuit of the embodiment, and the operation of the event shift register 23 will be described more concretely with reference to FIG. explain. The same components as those shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted here.

In FIG. 6, the comparator pulse generation circuit 22 outputs a pulse signal when one of the comparators in the comparator section 20 detects a designated event, and the pulse signal is output to each shift register 23 a of the event shift register 23. 23d to 23d are input as shift clock signals. Therefore, the comparator 20 at that time
The output states of a to 20d are fetched as 1-bit data into the corresponding shift registers, and the 4-bit comparator state is stored. The 4-bit data fetched at this time includes AND and OR information for each of the four events.

Furthermore, the comparator pulse generation circuit 2
2 detects each of the shift registers 2 when one of the comparators of the comparator unit 20 detects the designated event.
A pulse signal is output to 3a to 23d, and the output states of the comparators 20a to 20d at this time are shifted and stored as 1-bit data in the corresponding shift registers. In this way, the shift function of the shift registers 23a to 23d causes the event shift register 23 to store the time-series information of the designated event occurrence. In the case of the present embodiment, assuming that each of the shift registers 23a to 23d is composed of 6 bits, it is possible to detect the occurrence of a maximum of 6 stages of sequential events.

Here, the event detected by the comparator 20a is E1, the event detected by the comparator 20b is E2, the event detected by the comparator 20c is E3, and the event detected by the comparator 20d is E.
4, each bit of the parallel data of the shift register 23a is B10, B11, B12, B13, B14, B15,
Set each bit of parallel data of the shift register 23b to B2
0, B21, B22, B23, B24, B25, and the parallel data bits of the shift register 23c are set to B30, B3.
1, B32, B33, B34, B35, and the parallel data bits of the shift register 23d are B40, B41, B4.
If we set 2, B43, B44, B45 and shift from 0 to 5 of each subscript, the combination of events (E1 & E2 & E3 & E4) is (B10 & B20 & B30 & B4
It can be detected by the combinational logic of 0). In addition,
& Indicates AND designation.

Further, if> indicates sequential designation, the combination of events {E1>E3> (E2 & E4)} can be detected by the combination logic (B12 & B31 & B20 & B40). And also #
Is an OR designation, as an example of the case where the sequence is 5, {(E1 # E2)> (E2 & E3 & E
The combination of events 4)>E1>E4> (E3 # E4)> E1} is {(B15 # B25) & (B24 & B34)
& B44) & B13 & B42 & (B31 # B41) & B10}
Can be detected by the combinational logic, and this combinational logic can be further detected by {(B25 & B24 & B34 & B44 &
B13 & B42 & B41 & B10) # (B15 & B24 & B3
4 & B44 & B13 & B42 & B41 & B10) # (B25 &
B24 & B34 & B44 & B13 & B42 & B31 & B10)
# (B15 & B24 & B34 & B44 & B13 & B42 & B3
1 & B10)} can be detected by the combinational logic.

As described above, the combination of events is AN
Since it can be detected by the D-OR logic, the parallel data from each of the shift registers 23a to 23d is input to the event detection combination logic circuit 24 having the PLA structure, and the combination logic by the PLA of the event detection combination logic circuit 24 The combination of events to be detected can be detected at high speed. Also, a combinational logic circuit 2 for event detection
Since the circuit scale of 4 can be realized by the PLA structure,
High integration is possible.

FIG. 7 shows an example of a PLA map showing connection information of PLA by AND-OR logic in the event detection combination logic circuit 24 for detecting the combination of events in the case of the above sequence 5. It is a figure. In FIG. 7, "/" at the intersection of the signal lines is
It indicates that the intersection is connected, and the output of the OR logic becomes the output of the event detection combinational logic circuit 24.

Further, in the PLA map example of FIG. 7, when the comparators 20a to 20d detect the coincidence, the signal of "H" is output from the output of the comparator which detects the coincidence, and the "H" signal is input. "1" is stored in the shift register, and otherwise, each comparator 20a
20d outputs an "L" signal, and "0" is stored in the shift register to which the "L" signal is input. A combination of set events is detected. Then, the output of the OR logic in FIG. 7 becomes "1". The diagram showing the PLA map shown in FIG. 7 shows a part of the event detection combination logic circuit 24, and the input of the event detection combination logic circuit 24 is 24 as in this embodiment. In this case, there are 24 AND logic circuits shown in FIG.

Further, in the event detection circuit of the first embodiment, even when used in the trace control circuit 7 of FIG. 1, the operation principle is the same as that of the break circuit 5 described above except that the content of the detected event is different. The description is omitted because it is the same as when it is used.

Example 2. Next, FIG. 8 shows an example of a debug device which has a function of capturing and recording bus information of a microprocessor and debugs a microprocessor application system or the like using the event detection circuit of the second embodiment of the present invention. FIG. 9 is a schematic block diagram. First, the outline of a debug device using the event detection circuit of the second embodiment of the present invention will be described with reference to FIG. In FIG. 8, the same components as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 1 will be described.

8 is different from FIG. 1 in that the event detection circuit 4a in FIG. 1 is replaced with the event detection circuit 40 in the second embodiment of the present invention, and the break circuit 5 is replaced with the break circuit 50 accordingly. 1, the event detection circuit 4b according to the first embodiment of the present invention provided in the trace control circuit 7 in FIG. 1 is eliminated, and accordingly, the trace control circuit 7 is replaced with the trace control circuit 70, and the trace control circuit 70. Is connected to the event detection circuit 40, and therefore, the debug device 1 is changed to the debug device 10.

In FIG. 8, the event detection circuit 40 is
The operation of the target microcomputer is monitored and the occurrence of a specified condition, which is the address executed by the target microcomputer or the accessed data, is detected, and the break circuit 50 interrupts the emulation microcomputer control circuit based on the condition detected by the event detection circuit 40. It has a function for controlling the control function.

The trace control circuit 70 has a trace function of detecting the occurrence of the specified condition according to the set condition and recording the bus operation of the target microcomputer (emulation microcomputer in the debugger). , Controlling the address and controlling the recording start or end operation according to the set conditions. In the trace control circuit 70, the conventional event detection circuit or the event detection circuit 4b of the first embodiment described above is used.
In order to make the description of the event detection circuit of the second embodiment easier to understand, a circuit having an event detection function will be described here as a single block.

The event detection circuit 40 and the trace control circuit 70 are connected to the target system by a bus 9 composed of an address bus, a data bus, a control bus, etc., and the event detection circuit 40, the break circuit 50 and the trace are connected. The control circuit 70 is connected to the emulation microcomputer control circuit 3 via the emulator control MPU bus 8, and the break circuit 50 is connected to the emulation microcomputer control circuit 3 separately. The event detection circuit 40 is provided in the break circuit 50, and the trace control circuit 70 is connected to the event detection circuit 40, and outputs the write signal to the trace memory 6 and at the same time the event detection circuit 40. To the shift clock signal.

In the configuration as described above, FIG.
8 is a block diagram showing a sequential event detection circuit showing a second embodiment of the event detection circuit of the present invention for use in the event detection circuit 40 shown in FIG. 8 together with the trace memory 6 and the trace control circuit 70 of FIG. Therefore, the event detection circuit of the second embodiment of the present invention will be described while explaining the operation of performing operation control and operation observation in the debug device 10 shown in FIG. 8 with reference to FIG. In FIG. 9, the same components as those shown in the schematic block diagram of the debug device of FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

The event detection circuit 40 shown in FIG. 9 is different from the event detection circuit of the first embodiment shown in FIG. 4 in that the target of event detection is not the output signal from the comparator circuit, but the signal directly from the bus 9. Data to be traced is stored in a shift register, which comprises a shift register 23A forming an information storage means and an event detecting combination logic circuit 24A forming a combination detecting means. The shift clock signal to the shift register 23A is a trace It is shared with the write signal to the memory 6.

In FIG. 9, a trace function circuit 30 which forms a trace memory 6 and records an operation during execution of a target program, and a trace control circuit 70 which controls the start or stop of recording in the trace function circuit 30. The trace function control write circuit 31 is connected to the bus 9, and when the trace function control write circuit 31 detects the condition of a designated event, it controls the start or stop of recording in the trace function circuit 30.

The bus 9 is composed of a plurality of shift registers 23.
Each of the event shift registers 23A1 to 23An of A1 to 23An (n is a positive integer indicating the total number of shift registers) is connected to each of the shift registers 23A1 to 23An, and each of the shift registers 23A1 of the event shift register 23A is connected. 23 to 23An are connected to the trace function control write circuit 31, and a recording start signal from the trace function control write circuit 31 to the trace function circuit 30 is input to each shift register 23A1 to 23An of the event shift register 23A. At the same time, the recording start signal forms a shift clock signal for the shift registers 23A1-23An of the event shift register 23A.

The outputs of the shift registers 23A1-23An of the event shift register 23A are connected to the event detection combinational logic circuit 24A. The event detection combination logic circuit 24A has a PLA structure, and a desired combination of events can be detected by selecting a necessary combination. Each of the shift registers 23A
The respective event data stored in 1 to 23An are simultaneously output as parallel data to the event detecting combinational logic circuit 24A. Each of the shift registers 23A1 to 23An in the event shift register 23A is provided as many as the number of bits of the event data input from the bus 9. For example, the number of event data input from the bus 9 is 8
In the case of a bit, n of 23An is 8 and eight shift registers are provided.

In the above structure, when the trace function controlling write circuit 31 detects the data of the event of the specified condition, for example, the event of the specified condition from the bus 9, the recording start signal is sent to the trace control circuit 30. At the same time, the signal is output to the event shift register 23A as a shift clock signal. The trace function circuit 30 receiving the recording start signal records the data input from the bus 9 until the recording end signal is input, and the shift register 23A1 to 23An of the event shift register 23A receiving the shift clock signal, Event data input from the bus 9 is transferred to each shift register 23A1-23A.
One bit is recorded in An and, for example, when the data input from the bus 9 is 8 bits, one bit of the 8-bit signal is stored in time series in the eight shift registers.

The event detection combinational logic circuit 24A
In the above, in the event shift register 23A, each one of the shift registers 23A1 to 23An stored in time series is treated as one data, and the PLA structure is used to detect a necessary combination of the data. It is set. Event detection combinational logic circuit 24A
Detects the specified combination, the break circuit 50
The break circuit 50 outputs a break request signal to the emulation microcomputer control circuit 3.

As in the first embodiment, P in the PLA structure used in the event detecting combinational logic circuit 24A.
Since the LA plane can adopt a configuration in which its logical structure is changed by an SRAM-based switch matrix, the combination of events to be detected can be changed at any time by software. Also in this embodiment, emulation microcomputer control The circuit 3 changes the combination of events detected by the event detection combination logic circuit 24A via the emulator control MPU bus 8 at any time. The method of designating the event combination in the event detection combination logic circuit 24A is performed by the same method as in the first embodiment, and therefore its explanation is omitted here.

Next, the operation of detecting a combination of events using the event detection circuit of the second embodiment shown in FIG. 9 will be described with the operation control and operation observation of the debug device 10 of FIG. This will be described with reference to the flowchart of 10. In FIG. 10, first, in step S50
In the trace function control write circuit 31,
In the event detection circuit 40, the event combination to be detected is set by the emulation microcomputer control circuit 3 via the emulator control MPU bus 8 for each data of the respective specified conditions for detecting the intended event. The trace function control write circuit 31 uses the set data set above and the bus 9
A target event is compared with the address and data executed by the target microcomputer, and if a match with the setting data is detected, a predetermined event is detected.

Next, in step S52, when the trace function control write circuit 31 detects a predetermined event (YES), the trace function control write circuit 31 sends a recording start signal to the trace function circuit 30 in step S53. And the event shift register 23A
Then, the event detection pulse signal, that is, the shift clock signal is outputted to step S54. If the trace function control write circuit 31 does not detect a predetermined event in step S52 (NO), step S52 is performed.
Return to 51.

In step S54, the trace function circuit 30
Stores the data from the bus 9 until the trace function control write circuit 31 detects the recording end condition and the recording end signal is input, and the event shift register 2
Each of the shift registers 23A1 to 23An of 3A receives the event data input from the bus 9 from each shift register 23A.
The data is shifted one bit at a time from 1 to 23An and recorded, and in step S55, each data in each shift register 23A1 to 23An in the event shift register 23A is simultaneously output in parallel as parallel data to the event detection combination logic circuit 24A, and in step S55. Proceed to S56.

The combination logic circuit 24A for event detection is
If the set event combination is detected in step S56 and the set event combination is detected in step S57 (YES), an event combination detection signal indicating that the event combination set in step S58 is detected. Is output to the break circuit 50, and the present flow ends. If the event detection combination logic circuit 24A does not detect the set event combination in step S57 (NO), the process returns to step S50 to perform the processing of step S50 and thereafter.

As described above, in the debug device using the event detection circuit of the second embodiment, while recording the state change of the target microcomputer by the trace function,
Event detection can be realized by detecting the occurrence of a specified condition in the state change, and when the data change at the time of data access to a specific address in the target program operation causes a series of changes, it is regarded as an event. Can be detected.

In the first and second embodiments,
PLA for combinational logic circuits 24 and 24A for event detection
Although the structured device is used, a RAM may be used instead of the device, and in the second embodiment, a shift register having the same size as the number of recording steps of the trace memory 6 can be prepared. When it is difficult in terms of hardware, a configuration that provides a high-level event detection function within a limited range by using a comparator circuit for the circuit that generates the shift clock is also conceivable. As described above, the event detection circuit of the present invention is not limited to the above embodiment, and various modifications are conceivable, and it goes without saying that the scope of the present invention should be defined by the claims. Yes.

[0081]

As is apparent from the above description, according to the present invention, since the combination of events can be detected by AND-OR logic, the parallel data from each shift register has a PLA structure for event detection combination logic circuit. , And the combination logic of the event detecting combination logic circuit by the PLA can detect the combination of the events to be detected at high speed. Further, the circuit scale of the event detection combinational logic circuit can be realized with a PLA structure, and thus high integration is possible, so that it is easy to achieve high speed and high functionality as compared with the conventional technology. The circuit scale can be made compact.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an example of a debug device using an event detection circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation for controlling the operation of a target microcomputer by the debug device shown in FIG.

FIG. 3 is a flowchart showing an operation of observing the operation of the target microcomputer by the debug device shown in FIG.

FIG. 4 is a block diagram showing an event detection circuit according to the first exemplary embodiment of the present invention.

5 is a flowchart showing an operation of detecting a combination of events in the event detection circuit of the present invention shown in FIG.

FIG. 6 is a block diagram showing a configuration example of the event detection circuit of the first exemplary embodiment of the present invention shown in FIG.

FIG. 7: AN in combinational logic circuit for event detection
It is the figure which showed the example of the PLA map which showed the connection information of PLA by D-OR logic.

FIG. 8 is a schematic block diagram showing an example of a debug device using the event detection circuit of the second exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing an event detection circuit according to a second embodiment of the present invention.

10 is a flowchart showing an operation of detecting a combination of events in the event detection circuit of the present invention shown in FIG.

FIG. 11 is a block diagram showing a conventional event detection circuit.

[Explanation of symbols]

1, 10 Debugging device, 2 Emulation microcomputer, 3 Emulation microcomputer control circuit, 4a, 4
b, 40 event detection circuit, 5, 50 break circuit, 6 trace memory, 7, 70 trace control circuit, 8 emulator control MPU bus, 9 bus, 20
Comparator section, 20a, 20b, 20c, 20d
Comparator, 21 Detection event specification register, 22
Comparator pulse generation circuit, 23, 23A event shift register, 23a, 23b, 23c, 23d,
23A1 to 23An shift register, 24, 24A combination logic circuit 30 for event detection, trace function circuit,
31 Trace function control write circuit

Claims (8)

[Claims] 1. An event detection circuit for detecting a predetermined event, which stores input information in time series, and outputs the stored time series information at the same time in parallel, and from the information storage means. An event detection circuit comprising: combination detection means for detecting the occurrence of a predetermined combination of the input information by combining the information output in parallel. 2. The event detection circuit according to claim 1, wherein the information storage means comprises at least one shift register. 3. The event detection circuit according to claim 1, wherein the combination detection means has a PLA structure in which the input information is input to an AND array section. Event detection circuit. 4. An event detection circuit in a debug device having a function of fetching and recording bus information of a microprocessor and performing debugging of a microprocessor application system or the like, monitors the bus state of the microprocessor, and specifies a specified state. Bus state detection means for outputting a predetermined detection signal when detecting the signal, a signal output means for outputting a predetermined signal when the detection signal is output from the bus state detection means, and a predetermined signal from the signal output means Storage means having a function of storing the output signals from the bus state detecting means in time series, and simultaneously outputting the stored time series signal information in parallel, and the signal information output in parallel from the storage means. In the microprocessor by detecting the occurrence of a predetermined combination of the signal information. Event detection circuit, characterized in that a combination detection means for detecting the constant event. 5. The event detection circuit according to claim 4, wherein the storage means comprises a plurality of shift registers. 6. The event detecting circuit according to claim 4, wherein the combination detecting means has a PLA structure in which the signal information is input to an AND array section. Event detection circuit. 7. An event detection circuit in a debug device having a function of capturing and recording bus information of a microprocessor and performing debugging of a microprocessor application system or the like, monitors a bus state of the microprocessor, and detects the bus state. A plurality of comparator circuits that compare specified states and output a predetermined signal when they match, and a comparator pulse that outputs a pulse signal when one of the comparator circuits outputs the predetermined signal. An output circuit, a plurality of shift registers having a function of shifting by a pulse signal from the comparator pulse output circuit, respectively storing output states from the comparator circuits, and simultaneously outputting the stored information in parallel, Signal information output in parallel from each shift register Combination, by detecting the occurrence of a predetermined combination of the signal information, the event detection circuit, characterized in that it includes a combination logic circuit for detecting a particular bus state in the microprocessor. 8. The event detection circuit according to claim 7, wherein the combinational logic circuit has a PLA structure in which the signal information is input to an AND array section.