JPH04237348A - Memory accessing device - Google Patents

Abstract

PURPOSE:To reduce the size or the like of a memory accessing device by forming a resident area and plural non-resident bank areas in a large capacity memory module having an area exceeding a CPU memory space and using these areas via an address converter. CONSTITUTION:The inside of a large capacity RAM IC 130 is divided into four areas, an area 131 is a resident RAM area and residual areas 132 to 134 are respectively allocated to non-resident bank memory areas. An address converter 120 is connected between a mu-CPU 100 and the large capacity RAM IC 130, an address from the mu-CPU 100 and data indicating an area are inputted and converted into an address corresponding to the RAM IC 130 and the converted result is outputted.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a large-capacity memory with an area exceeding the address space that can be directly addressed by the CPU.
The present invention relates to a memory access device for effective use by a CPU. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

0002

[Prior Art] Conventionally, as a method of using memory whose area is extended beyond the address space that can be directly addressed by the CPU, a so-called bank switching method has been used, in which this extended area is switched and inserted into the CPU's address space. It is being FIG. 4(a) shows an example of the configuration of a system that allows expansion of the memory area using this bank switching method. Same figure (
In a), 100 is a microprocessor (μCPU) that can handle 8-bit and 16-bit data.
(also abbreviated as "A0" to "A19") has an address space of 1 Mbyte by providing 20 address lines (bits) A0 to A19. In this example, the μCPU 100 uses RA as a memory to allocate variables within its own memory space.
M101, a register 102 as a memory that temporarily stores input/output data for hardware control, a ROM 103 as a memory that stores programs, #1 to # as a memory that stores large-scale data, files, etc.
3 bank memories 104, 105, each having the same capacity.
106. Note that 108 is a 20-bit width address bus, 109 is a 16-bit width data bus, and 107 is a 20-bit width address bus.
is a bank switch for selecting one of the bank memories 104 to 106 and connecting it to the bus.

[0003] Here, RAM 101, register 102, R
The OM103 is a resident area that can be accessed directly from the μCPU 100 at all times, but the bank memories 104 to 10
6, since the μCPU 100 does not have remaining memory space that can accommodate all three bank memories, the bank switch 107 switches the bank memories 104 to
106 causes the selected bank memory to be directly addressed within the memory space of μCPU 100.

FIG. 4(b) shows the μCPU 100 shown in FIG. 4(a).
An example of address space allocation (memory map) is shown below. In this case, the 1M byte space 110 is divided into four areas 111 to 114 of 256K bytes each, and this area 111
into the address area of the RAM 101, the area 112 into the area where the bank memories 104 to 106 are allocated, the area 113 into the area of the register 102 for hardware control, and the area 114 into the area of the ROM 103 where the program is stored. Assigned.

[0005]

In the conventional configuration as shown in FIG. 4, RAM 101, ROM 103, and bank memories 104, 105, and 106 were each composed of separate memory chips. That is, for example, the RAM 101 and bank memories 104 to 106 each have an RA of 8 bits x 64K.
Consists of 4 Mics, ROM103 is 8 bits x 1
It was composed of two 28K ROMics, and the register 102 was composed of a frame memory for a graphics screen and the like. In this way, in the example of FIG.
A total of 16 RAMics were required to configure M101 and bank memories 104 to 106.

[0006] In recent years, the capacity of RAMic has increased significantly, and 8
With the advent of RAMics such as 512K bits and 1M bits, the price/bit has dropped significantly. However, in the conventional configuration, RAMic is individually allocated to each area 111, 112, so 8 bits x 12
Even if a cheap RAMic with 8K or higher were to appear, there would be little merit in adopting it. For example, RAM101 has 8 bits x 51
If you use a 2K RAMic, the data width is 1
Since it is 6 bits, two are used, and only 256K bytes of the 1M byte of the address space are used.
3/4 of the memory capacity will be wasted. SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a memory access device for effectively utilizing a large-capacity RAMic that exceeds the size that can be managed by a μCPU.

[0007]

[Means for Solving the Problems] In order to solve the above problems, a memory access device according to claim 1 provides a CPU (1
In a computer system that has memory beyond the memory space that can be directly managed by the CPU (e.g. 00, RAMic 130, etc.), is provided between the CPU and the memory module, and is provided between the CPU and the address (RAMic 130, etc.).
A18, A19, etc. of the address bus 108) and data indicating the area (data B1, B0, etc. set in the bank selection register 122 via the data bus 109) are input (via the conversion table 123, etc.) to the memory. Address to module (RAM address bus 12
RA18, RA19 in 1, chip select signal (inverted CS), etc.) and an address converter (address converter 120, etc.), and

[0008] In the memory access device according to claim 2, in the memory access device according to claim 1, ``the address translation means includes a memory module having a resident area for the CPU, and a memory access device according to the first aspect. When the address for this resident area is issued, the data indicating the area is ignored and the address for this resident area is converted and output.''

[0009]

[Operation] A RAMic having a large continuous space is divided into spaces, and in addition to providing a resident area for the μCPU within this space, the remaining area is used as a plurality of non-resident areas. And for this purpose, μCPU and large capacity RAMic
An address converter with bank switching function is placed between them.

0010

[Embodiment] Next, an embodiment of the present invention will be described based on FIGS. 1 to 3. FIG. 1 is a system configuration diagram as an embodiment of the present invention, and is an example in which the functions shown in FIG. 4 are realized by the present invention. In Figure 1, 130 indicates two 8-bit x 512K RAMs (
A large-capacity RAMic with a memory space of 1MB),
Inside this, there are four areas 131 to 1 of 256K bytes each.
The area 131 with addresses 00000 to 3FFFF is the resident RAM area corresponding to the RAM 101 in FIG. 4(a), and the remaining areas 132, 132, and 133 are the bank memories 104 to 106 in FIG. 4(a), respectively. It is allocated to the non-resident bank memory areas #1 to #3 corresponding to the non-resident bank memory areas. In order to realize the same function as in FIG. 4, an address converter 120 is provided between the μCPU 100 and the large-capacity RAMic 130 in FIG.

FIG. 2 is a block diagram showing the configuration of this address converter 120. That is, the address converter 120 is composed of a bank selection register 122 and a conversion table 123. Here, the address converter 120 is the μCPU 10
0 via the data bus 109 at the timing of the bank register write signal 124, and stores it in the bank selection register 122. In this example, bank selection register 122 is composed of a 2-bit register. The conversion table 123 inputs the output data B1, B0 of the bank selection register 122 and the most significant two bits A19, A18 of the address bus 108, and converts the data into the large capacity RAMi.
The chip select signal in the address bus 121 for c (that is, the signal for enabling/disabling the large-capacity RAMic 130, the sign is inverted CS) and the most significant two bits of address signals RA19 and RA18 are output. Also μCPU10
Lower 18 bits A0 to A in the 0 address bus 108
17 is output as is for the lower 18 bits RA0 to RA17 in the address bus 121 of the large capacity RAMic 130.

FIG. 3 shows a truth table for the conversion of the conversion table 123. In other words, the value of the output data (B1, B0) of the bank selection register 122 is (0, 1) for the #1 bank memory, the value (1, 0) for the #2 bank memory, and the value (1, 0) for the #2 bank memory.
, 1) respectively select the #3 bank memory. Furthermore, when the address buses A19 and A18 of the μCPU 100 are both "0", the large capacity RAMic 130 is selected regardless of the value of the data bus 109 and therefore the output values B1 and B0 of the bank selection register 122 (chip select signal (inverted CS ) is “1”), and RAM address bus 12
Both the highest addresses A19 and A18 of 1 become "0", and the RAM area 131 in the large capacity RAMic 130 is accessed. As a result, the large-capacity RAMic 130 is equipped with both resident and non-resident memory areas, and the μCPU 10
It can be effectively used as non-contiguous memory starting from 0. Figure 1 is functionally equivalent to the conventional configuration in Figure 4, and when the large capacity RAMic used is 8 bits x 512K, the conventional 8 bits x 64K RAMic chips are reduced from 16 chips to 2 chips. This allows memory to be smaller and lower in price.

In the above embodiment, the conversion table 123
The most significant bit A1 of 1M byte space as input and output of
9, A18 is adopted, but when using a static type RAMic, any two bits can be used. However, in this case, the areas 131 to 134 in the large-capacity RAMic 130 do not exist as a block, but are scattered in various places. Furthermore, in the above description, signals related to reading and writing to the memory 130 are omitted.

[0014]

Effect of the Invention According to the invention related to claim 1, μCP
In a computer system having memory beyond the memory space that U100 can directly manage, the μCPU 10
A large-capacity RAMic 130 as a memory module that includes an area exceeding the memory space of 0, has the required total memory capacity, and has continuous addresses, and the μCPU 10
0 and the memory module 130, and the μ
Address from CPU 100 (A of address bus 108
18, A19) and data indicating the area (data bus 109
Data B set in the bank selection register 122 via
1, B0), and then input the address (RA
RA18, RA19 in the M address bus 121, and an address converter 120 that converts the signal into a chip select signal (inverted CS) and outputs the signal.

[0015]
According to the invention related to claim 2, in the memory access device of claim 1, the address converter 120 is configured such that the memory module 130 has a resident area for the μCPU 100, and the μCPU 100 has an address for this resident area. When this occurs, the data indicating the area is ignored and the address for this resident area is converted and output, so the following effects can be obtained. 1) By using a large capacity RAMic, the system space can be reduced and the device can be made smaller. 2)
(1) allows the cost of the entire memory to be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration as an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing an example of the configuration of the address converter in FIG. 1;

[Figure 3] Diagram showing the truth table of the conversion table in Figure 2

[Fig. 4] Block diagram showing a conventional configuration corresponding to Fig. 1

[Explanation of symbols]

100 μCPU 102 Register 103 ROM 108 Address bus 109 Data bus 120 Address converter 121 RAM address bus 122 Bank selection register 123 Conversion table 124 Bank register write signal 130
Large capacity RAM 131 Resident RAM area

Claims (2)

[Claims] Claim 1: In a computer system having memory beyond a memory space that can be directly managed by a CPU, the C
A memory module that includes an area exceeding the memory space of the PU, has the required total memory capacity, and has consecutive addresses, and is provided between the CPU and the memory module, and is provided with data indicating the address and area from the CPU. What is claimed is: 1. A memory access device comprising: address converting means for inputting an address, converting it into an address for the memory module, and outputting the converted address. 2. The memory access device according to claim 1, wherein the address translation means has a resident area for the CPU, and the memory module has a resident area for the CPU.
A memory access device characterized in that when U issues an address for this resident area, data indicating the area is ignored and the address for this resident area is converted and output.