JP2008003867A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to expand the memory of a microcomputer without deteriorating performance or code efficiency by changing the ratio of sizes of memories for storing a program code and a data code at the stage of system development. <P>SOLUTION: An address translation circuit 102 is provided. Either an inputted address from a CPU 101 or an address formed by adding a bias value 130 is selected by an identifying signal 105 that identifies an instruction fetch of the CPU 101/data access. The memory size of the memory 103 is expanded by performing addressing of the program code region or the data code region of the memory 103. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory access area expansion circuit technique and relates to a configuration suitable for application to a microcomputer.

  As the functions of a system equipped with a microcomputer improve, the control program size of the microcomputer has increased. For this reason, there is a demand for expanding the size of memory that can be used in a microcomputer.

  The method of realizing the expansion of the memory size by increasing the number of bits of the address signal of the CPU involves a problem that the amount of change work is large because the system change including the instruction code is involved, and the development period and cost increase.

  For this reason, a method for realizing expansion of the memory size while suppressing an increase in cost has been proposed and implemented.

  FIG. 5 is a block diagram showing a main part of a circuit configuration example of a conventional microcomputer for expanding the memory size. The microcomputer 900 includes a CPU 901, a control register 902, an address converter 903, a memory 904 for storing programs and data, and the like. An address bus output signal 905 output from the CPU 901 is input to the control register 902 and the address converter 903. The address conversion control signal 906 output from the control register 902 is input to the address converter 903. A memory address bus input signal 907 output from the address converter 903 is input to the memory 904. The data bus 908 is connected to the CPU 901, the control register 902, and the memory 904.

  FIG. 6 shows a memory map of the microcomputer 900 shown in FIG. The memory space that can be specified by the address of the CPU 901 is 911, whereas the physical memory space of the memory 904 is 912. The physical memory space 912 of the expanded memory 904 is larger than the memory space 911 that can be directly accessed by the CPU 901.

  Therefore, the area 914 in the physical memory space 912 of the memory 904 can be directly accessed without performing address conversion by the address output from the CPU 901. However, since the area 915 of the physical memory space 912 of the memory 904 cannot be directly accessed, an operation for converting the address output by the CPU 901 into an address corresponding to the area 915 is required.

  FIG. 7 shows a memory access operation waveform of the microcomputer 900. Here, in FIG. 6, a case will be described in which the area 915 is accessed after the area 914 of the physical memory space 912 is accessed, and the area 914 is further accessed.

  The CPU 901 accesses, for example, the memory addresses A0 and A1 of the area 914 that can be accessed without address conversion, then accesses the address D0 of the control register 902, and sets the address conversion control signal 906 to the high level.

  While the address conversion control signal 906 is at a high level, the address bus output signals B0 and B1 output from the CPU 901 are converted into addresses C0 and C1 for accessing the area 915 by the address converter 903, for example. Next, the CPU 901 accesses the address D0 of the control register 902 and sets the address conversion control signal 906 to the low level. Thereafter, the CPU 901 accesses, for example, the memory addresses A2 and A3 in the area 914 that can be accessed without address conversion.

  As described above, the conventional method described above requires access to the control register 902 when accessing the area 915 of the physical memory space 912 in FIG. 6, resulting in a decrease in performance and a decrease in code efficiency. was there.

Also, there is a technique for memory expansion, in which a plurality of memories are not assigned to different addresses, but at least a part of them is assigned to an overlapping address, and the memory is selected by using a CPU status signal so that the performance is not deteriorated. (For example, refer to Patent Document 1).
JP-A-8-63392 (page 4, FIG. 1)

  However, in the memory expansion method for increasing the total memory capacity as in Patent Document 1, the size of the program code and data code required for the individual memory capacity (memory size) selected by the status signal varies in the system development stage. Sometimes it becomes difficult to change flexibly. For this reason, an additional memory capacity is provided for each memory, which increases the chip area and raises the cost.

  The present invention has been made to solve the above problems, and it is possible to change the ratio of the memory size of the memory for storing the program code and the data code in the system development stage, and to expand the memory without degrading the performance and code efficiency. An object is to provide a microcomputer to be used.

  In order to achieve the above object, a microcomputer of the present invention receives a CPU, a first memory address and a status signal from the CPU, and has a memory larger than a memory space that can be specified by the first memory address. Address conversion means for outputting a second memory address that can designate a space based on the status signal, and a memory that is addressed by the second memory address output from the address conversion means and reads an instruction code or a data code The value of at least a part of the second memory address is the same as the value of the first memory address.

  According to the present invention, it is possible to change the ratio of the memory size of the memory for storing the program code and the data code in the system development stage, and compared with the memory size that can be directly accessed by the CPU without deteriorating the memory access performance and code efficiency. A microcomputer capable of expanding the memory size can be provided.

  Examples of the present invention will be described below.

  A microcomputer according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a circuit configuration of a microcomputer having a memory expansion function according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an address conversion circuit for realizing the memory expansion function. FIG. 3 is a memory map diagram of the microcomputer according to the embodiment of the present invention. FIG. 4 is an operation waveform diagram of the memory access operation of the microcomputer according to the embodiment of the present invention. The drawing used in this embodiment is abbreviated to the extent necessary for explanation.

  A microcomputer 100 shown in FIG. 1 includes a CPU 101 that executes a program, an address conversion circuit 102 that converts a memory address output from the CPU 101 in accordance with a status signal from the CPU 101, and a memory that stores program codes and data codes. 103.

  A CPU address bus output signal 104 output from the CPU 101 and an access identification signal 105 for identifying instruction fetch / data access are input to the address conversion circuit 102. The memory address bus input signal 106 output from the address conversion circuit 102 is input to the address input of the memory 103. The data bus 107 is connected to the CPU 101 and the memory 104.

  FIG. 2A shows a configuration of the address conversion circuit 102, which includes an adder 110, a 2-input 1-output selector 120, and a bias value 130 indicating a preset extension size.

  The address bus output signal 104 output from the CPU 101 is input to the data inputs of the adder 110 and the selector 120, respectively. The adder 110 inputs and adds the input address bus output signal 104 and the output signal 111 from the bias value 130, and outputs the addition result as an address signal 112.

  The selector 120 receives the address signal 112 from the adder 110 and the signal 113 (with the same bit width as the address signal 112) expanded by adding “0” to the upper side of the address bus output signal 104, and receives data from the CPU 101. The address identification signal 105 for identifying the instruction fetch / data access output from is selected and output from either one of the two addresses and output to the memory 103 as the memory address bus input signal 106. The bias value 130 of the address conversion circuit 102 is preset with a value that allows the memory 103 to access a size expanded from the memory size that the CPU 101 can directly address.

  Next, details of the operation of the address conversion circuit 102 when the CPU 101 accesses a program code or data code from the memory 103 will be described with reference to FIGS. 3 and 4.

  When an application program developed by the user becomes larger than the memory size accessible by the CPU 101, the size of the memory 103 is expanded so that the program can be stored. As a result, a physical memory space 202 larger than the memory space 201 that can be directly accessed by the CPU 101 is formed in the memory 103 as shown in the memory map of FIG.

  In the physical memory space 202 of the memory 103, the program code is stored in the area 204 and the data code is stored in the area 205. In the present invention, an area 206 where the program code and the data code overlap is provided.

  An area that can be directly accessed by the address bus output signal 104 output from the CPU 101 is an area 204 in the physical memory space 202 of the memory 103. On the other hand, when accessing the area 205 of the physical memory space 202 of the memory 103, the address bus output signal 104 output from the CPU 101 is converted into an address corresponding to the area 205 by the address conversion circuit 102.

  For example, when the address bus width of the address bus output signal 104 of the CPU 101 is 16 bits and the memory capacity of the expanded memory 103 is 96K words (main area 64K + expansion unit 32K), the program code of FIG. 3 is stored. The leading address N1 of the area 204 is “00000” H (H: indicates a hexadecimal number), and the final address N3 is “0FFFF” H. Further, if the head address N2 of the area 205 for storing the data code is, for example, “08000” H, the final address N4 is “17FFF” H. Accordingly, in this example, a value of “8000” H is set as the bias value 130.

  Next, the operation of the microcomputer 100 according to the embodiment will be described with reference to FIG.

  In the memory access operation transition of FIG. 4, after the CPU 101 of the microcomputer 100 performs the read access of the program code stored in the area 204 of the memory 103, the read access of the area 205 in which the data code is stored is performed again. An example of reading the program code in the area 204 is shown.

  First, in the first and second cycles, the CPU 101 outputs, for example, addresses A0 and A1 as the address bus output signal 104, and outputs a low-level access identification signal 105 that identifies instruction fetch / data access for reading the program code. To do.

  Since the access identification signal 105 is Low, the selector 120 of the address conversion circuit 102 selects the signal 113 obtained by adding “0” to the higher address to the address bus output signal 104 from the CPU 101, and the memory address bus input signal 106. To the memory 103. Therefore, the address bus output signal 104 from the CPU 101 is input to the address input of the memory 103 without being subjected to address conversion. In the memory 103, the program code addressed according to the addresses A 0 and A 1 and stored in the area 204 is read into the CPU 101 via the data bus 107.

  Next, in the third and fourth cycles, the CPU 101 outputs addresses B0 and B1, for example, and outputs a high-level access identification signal 105 for identifying instruction fetch / data access for reading the data code.

  Since the instruction fetch / data access identification signal 105 is High, the selector 120 of the address conversion circuit 102 inputs and adds the address value of the address bus output signal 104 from the CPU 101 and the value of the output signal 111 of the bias value 130. The address 112 output from the adder 110 is selected and output to the memory 103 as the memory address bus input 106. Thus, the addresses B0 and B1 output from the CPU 101 are converted into, for example, addresses C0 and C1 by the address conversion circuit 102 and input to the address input of the memory 103. In the memory 103, the data code addressed according to the addresses C 0 and C 1 and stored in the area 205 is read into the CPU 101 via the data bus 107.

  In the fifth and sixth cycles, the CPU 101 outputs addresses A2 and A3, for example, and outputs a low-level access identification signal 105 for identifying instruction fetch / data access for reading the program code.

  In the selector 120 of the address conversion circuit 102, since the access identification signal 105 for identifying instruction fetch / data access is Low, the addresses A2 and A3 of the address bus output signal 104 from the CPU 101 are the same as in the first and second cycles. The address is input to the memory 103 without address conversion. In the memory 103, the program code addressed according to the addresses A 2 and A 3 and stored in the area 204 is read into the CPU 101 via the data bus 107.

  In this way, when accessing the program code area and the data code area, the microcomputer 100 does not require execution of a special instruction for the address conversion circuit 102 or an access cycle for the memory 103. Can be accessed and performance degradation and code efficiency degradation can be avoided.

  In addition, when the microcomputer 100 including the address conversion circuit 102 of this embodiment described above is used, a user can directly access the CPU 101 by developing an application program by distinguishing a program (instruction) code area and a data code area by program development. The application program having a size exceeding the memory size to be stored can be stored in the memory 103.

  Also, even if the user changes the program at the development stage and the area size of the program code is changed, the address conversion circuit and the like are changed as long as the sum of the area with the data code area does not exceed the memory capacity size of the memory 103. This eliminates the need for user program development.

  In addition to storing constants and pattern data such as voice data and character code image data in the data code area, for example, if a sine wave table (time and amplitude value) is stored, when calculating the current value in motor control By referring to the above, it is possible to realize a high-speed response, to reduce the program code for calculation, and to easily adjust the area ratio between the program code and the data code.

  The present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the spirit of the invention.

  For example, like the address conversion circuit 102 shown in FIG. 2B, a selector 120 is provided on the input side of the adder 110, and the selector 120 has an output signal 111 of a bias value 130 and a value of 0 (zero). The signal 114 is input, and either one of the inputs may be selected by the access identification signal 105 for identifying the instruction fetch / data access, and the signal 115 may be output and input to the adder 110. In this case, the output of the adder 110 becomes the memory address bus input 106 and is input to the memory address of the memory 103. By doing so, the input destination of the CPU address bus output signal 104 is one place in the adder 110 in the address conversion circuit 102, and the load on the address output driver of the CPU 101 is reduced, thereby speeding up the microprocessor and reducing the power consumption. In addition, the circuit width can be reduced by reducing the bit width of the selector 120 by 1 bit.

The block diagram which shows the structure of the Example of the microcomputer which concerns on this invention. FIG. 3 is a block diagram showing first and second configurations of an address conversion circuit according to the present embodiment. The figure which shows the memory map of the microcomputer of a present Example. The figure which shows an example of the operation | movement transition of the microcomputer of a present Example. The block diagram which shows the structure of the conventional microcomputer. The figure which shows the memory map of the conventional microcomputer. The figure which shows an example of the operation | movement transition of the conventional microcomputer.

Explanation of symbols

100, 900 Microcomputer 101, 901 CPU
102 Address conversion circuit 103, 904 Memory 104, 905 CPU address bus output signal 105 Instruction fetch / data access identification signal 106, 907 Memory address bus input signal 107, 908 Data bus signal 902 Control register 903 Address converter 906 Address conversion control signal 110 Adder 120 Selector 130 Bias Value 201 CPU Memory Space 202 Memory Memory Space 203 Memory Space 204 Directly Accessible by CPU 204 Program Code Area 205 Data Code Area

Claims (5)

CPU,
A first memory address and a status signal from the CPU are input, and a second memory address that can designate a memory space larger than a memory space that can be designated by the first memory address is output based on the status signal. Address translation means;
A memory that is addressed by the second memory address output from the address converting means and reads an instruction code or a data code, and at least a part of the value of the second memory address is a value of the first memory address A microcomputer characterized by having the same value. The address conversion means includes
An adder circuit for adding the first memory address and a predetermined value;
A memory address obtained by adding one or more digits “0” to the upper side of the first memory address to expand the bit width and a memory address that is an addition output of the adder circuit are input. The microcomputer according to claim 1, further comprising: a selector that outputs one of the two input memory addresses as the second memory address. The address conversion means includes
A selector that receives a predetermined value and “0”, and outputs one of the two input values according to the status signal;
An adder circuit for adding the output value of the selector and the first memory address to generate the second memory address;
The microcomputer according to claim 1, further comprising:   4. The microcomputer according to claim 2, wherein the status signal output from the CPU is a signal capable of identifying whether it is instruction fetch or data access. CPU,
A memory address generated by adding the first memory address output from the CPU and a fixed value greater than 0 and less than the maximum value of the first memory address; and the upper side of the first memory address One of the memory addresses in which the bit width is expanded by adding at least one digit bit “0” to the memory is selected by a status signal that can identify whether the instruction fetch or data access is output from the CPU. Or one of the fixed value and “0” is selected by the status signal, and the output value and the first memory address are added to generate the second memory address. When,
A memory having a memory capacity larger than a memory capacity that is addressed by the second memory address output from the conversion circuit and can be specified by the first memory address;
A microcomputer in which an address area of the memory accessible by the CPU at the time of fetching an instruction partially overlaps an address area of the memory accessible at the time of data access.

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