JP2002358236A - Information processing equipment, memory management unit, address translation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower power consumption increasingly. SOLUTION: A carry signal output circuit 5, when a logical address is newly written into an address counter 2 in an initialized state, and when carrying-over from a lower part to an upper part of the logical addresses occurs, outputs a carry signal. When the carry signal is outputted, a MMU(memory management unit) 6 reads, from the address counter 2, the upper part of the logical addresses to translate it into an upper part of the physical addresses. The translated upper part of the physical addresses is held in a translated value register 8 and is sent to a selection circuit 7. The selection circuit 7 selects the upper part of the physical addresses outputted from the MMU 6 according to the carry signal and outputs the upper part. Meanwhile, when the carry signal is not outputted, the MMU 6 does not operate. The selection circuit 7 selects the upper part of the physical addresses held in the translated value register 8 to output the upper part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device mounted on an information processing device and a memory management unit (MMU) mounted on the address conversion device, and more particularly to a power consumption for converting a logical address into a physical address. The present invention relates to a configuration for achieving reduction.

[0002]

2. Description of the Related Art In a battery-driven information processing apparatus such as a portable terminal, it is important to minimize power consumption. In order to perform memory management, the information processing device
Normally, an address translation device is mounted, and each data processed by the processor mounted on the information processing device is converted into a physical address by a logical address assigned to the data, and the physical address indicated by the physical address Loaded on memory.

[0003] The address translator is equipped with a circuit comprising a memory element called a memory management unit (MMU). When operating the MMU for address translation, a large amount of power is consumed to drive many circuit elements. Therefore, it is desired to reduce the power consumption of the processor by minimizing the operation of this circuit as much as possible in a battery-driven information processing apparatus.

For example, Japanese Patent Application Laid-Open No. Hei 10-260900 discloses that, regarding an instruction address with a slow page change, a once converted physical page address is saved in a register and compared with a subsequently input logical page address. When it is determined that the range is the same page address range, the saved physical page address is repeatedly used to
A data processing device for reducing the number of operations of U is disclosed.

[0005]

SUMMARY OF THE INVENTION As in this conventional example,
It is desirable for an information processing apparatus, particularly a battery-driven apparatus, to reduce the power consumption of a processor by reducing the number of operations of an MMU.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an information processing device, a memory management unit, and an address translation device capable of further reducing power consumption. To provide.

[0007]

In order to achieve the above object, an information processing conversion device according to a first aspect of the present invention is an information processing conversion device for converting an upper part of a logical address into an upper part of a physical address. A logical address holding unit for sequentially writing logical addresses to be converted, the logical address holding unit comprising: a logical address generating unit configured to generate a physical address from an upper part of the converted physical address and a lower part of the logical address; A carry signal that outputs a carry signal when a logical address is newly written, or when a carry from the lower part to the upper part of the logical address occurs when the logical address is written. Means, and the address conversion device operates only when a carry signal is output from the carry signal output means. A memory management unit for reading an upper part of the logical address written to the logical address holding means and converting the logical address into an upper part of the physical address, and a conversion value holding means for holding an output value from the memory management unit as a conversion value A physical value for selecting and outputting the output value from the memory management unit when the carry signal is output from the carry signal output means, and otherwise selecting and outputting the conversion value held in the conversion value holding means. An address high-order section selecting means, and when a carry signal is not output from the carry signal output means, a physical address is generated by the converted value and a lower part of a logical address without operating the memory management unit. Is what you do.

Further, the memory management unit according to the present invention is a memory management unit which converts a high-order part of a logical address input as an address conversion target into a high-order part of a physical address and outputs the same. Based on a divided address conversion table formed by dividing an address conversion table holding the upper part of an address in association with a plurality of bits and a bit value forming the upper part of an input logical address, only one of the divided addresses is used. A table selecting means for selecting a conversion table, and operating only the divided address conversion table selected by the table selecting means at the time of converting the upper part of the input logical address.

[0009] Further, an address translation device according to the present invention comprises:
A memory management unit according to the above invention is mounted.

An information processing apparatus according to another aspect of the present invention uses the address translation apparatus for converting an instruction logical address, and further incorporates the address translation apparatus according to the invention for converting a data logical address. .

[0011]

Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of the information processing apparatus according to the present invention. FIG. 1 shows an address translation device 1 and a processor core unit 21 having a configuration required to execute a characteristic address translation process in the present embodiment among the information processing devices. The address translation mechanism in the embodiment has a circuit configuration suitable for address translation for instructions. Logical addresses are sequentially written to the address counter 2 by the adders 3 and 4. Each adder 3, 4
The logical address to be converted is generated by adding a predetermined address addition value to the logical address held in the address counter 2. The adders 3 and 4 are provided in each of the upper part and the lower part of the logical address. For example, assuming that the address translation device 1 is mounted on an information processing device that uses a 32-bit machine to make one physical page 4 Kbytes, the adder 3 adds the upper 20 bits of the logical address, and 4 is the lower 1 of the logical address
Perform 2-bit addition. The carry signal output circuit 5 outputs a carry signal when a carry from the lower part to the upper part of the logical address occurs as a result of the addition by the adder 4. Further, the carry signal output circuit 5 also outputs a signal when a logical address is newly written in the address counter 2 in the initialized state. This signal is also referred to as a carry signal for convenience. The carry signal is input to a memory management unit (MMU) 6 and a selection circuit 7.

The MMU 6 reads the upper part of the logical address written in the address counter 2, converts it to the upper part of the physical address, and outputs it. This output value is input to the selection circuit 7 and the conversion value register 8. The conversion value register 8 holds the upper part of the physical address output from the MMU 6 as a conversion value. The selection circuit 7 selects and outputs one of the output value from the MMU 6 and the conversion value held in the conversion value register 8. This output value is written to the upper part of the physical address register 9. Further, in the lower part of the physical address register 9, the lower part of the logical address held in the address counter 2 is written as it is as the lower part of the physical address.

A feature of this embodiment is that a carry signal output circuit 5 is provided to transmit a carry signal to the MMU 6 and the selection circuit 7. Since the operation of the MMU 6 is controlled in accordance with the presence or absence of the carry signal, the number of operations of the MMU 6 can be reduced. Hereinafter, the operation in the present embodiment will be described.

First, the address counter 2 in the initial state
When a logical address is written in the carry signal, the carry signal output circuit 5 outputs a carry signal. The MMU 6 reads the upper part of the logical address from the address counter 2 in this instruction fetch cycle in response to the input of the carry signal, and converts the upper part of the physical address to the upper part.
The upper part of the converted physical address is held in the converted value register 8 and sent to the selection circuit 7 at the same time.

The selection circuit 7 receives the carry signal from the MMU 6 in this instruction fetch cycle.
The upper part of the physical address output from is selected and output. This output value is written to the upper part of the physical address register 9. Further, in the lower part of the physical address register 9, the lower part of the logical address held in the address counter 2 is written as it is as the lower part of the physical address. As described above, the logical address written in the address counter 2 is converted into a physical address. Note that this operation itself does not lead to lower power consumption because the MMU 6 is operating. Next, a characteristic operation in the present embodiment performed thereafter will be described.

The adders 3 and 4 generate a logical address to be converted by adding a predetermined address addition value to the logical address held in the address counter 2 and write the logical address into the address counter 2. At this time, it is assumed that no carry from the lower part to the upper part of the logical address has occurred. At this time, the carry signal output circuit 5 does not output a carry signal.

MMU 6 does not operate in this instruction fetch cycle because a carry signal is not input. Thus, MMU 6 in the present embodiment is controlled to operate only when a carry signal is input. The selection circuit 7 selects and outputs the converted value held in the converted value register 8, that is, the upper part of the physical address in this instruction fetch cycle because the carry signal is not input. This output value is written to the upper part of the physical address register 9. Further, in the lower part of the physical address register 9, the lower part of the logical address held in the address counter 2 is written as it is as the lower part of the physical address. As described above, the logical address written in the address counter 2 is converted into a physical address.

As described above, when the carry from the lower part to the upper part of the logical address does not occur, the conversion from the logical address to the physical address can be performed without operating the MMU 6. Thereby, low power consumption can be achieved.

Subsequently, when a logical address is sequentially written into the address counter 2 and a carry occurs, the carry signal output circuit 5 outputs a carry signal. The operation at this time is the same as when the logical address is written to the address counter 2 in the initial state, and thus the description is omitted.

According to the present embodiment, when an initial state or a carry occurs, the MMU 6 is operated to perform address conversion, and the upper part of the converted physical address is held. When no carry occurs, the MMU 6 is prevented from operating by using the upper part of the held physical address. In the present embodiment, whether the held conversion value can be used,
That is, since whether or not to operate the MMU 6 can be determined based on whether or not a carry occurs, it is not necessary to use a power consuming circuit such as a comparison circuit as a component for the determination. This can further reduce power consumption.

Embodiment 2 FIG. In the first embodiment, the number of operations of the MMU 6 can be reduced by focusing on the presence or absence of a carry from the lower part to the upper part of the logical address. Therefore, it can be said that the device configuration is suitable for an instruction in which there is little chance of carry-up due to the simple increase of the address continuously.

However, the first embodiment is intended to reduce the total power consumption by reducing the number of operations of the MMU 6, and the power consumption during the operation of the MMU 6 itself is the same as the conventional one. Thus, the present embodiment is characterized by providing an MMU that can reduce the power consumption during operation.

In general, the MMU has a single address conversion table for holding the upper part of the physical address in association with the upper part of the logical address, and stores the bit value constituting the upper part of the input logical address. , The upper part of the physical address is obtained by subtracting this table. Since this address conversion table is formed by circuit elements, the circuit elements are driven and power is consumed when the MMU 6 operates. The present embodiment is characterized in that the address conversion table is divided into a plurality of parts, and when the address is converted, only the corresponding divided table is operated to reduce power consumption.

FIG. 2 is a block diagram showing the configuration of the address translator 10 equipped with the MMU according to the present embodiment, and FIG. 3 is a diagram showing the internal configuration of the MMU according to the present embodiment. In FIG. 2, a logical address register 11 is a logical address holding unit in which a logical address to be converted is written. The previous logical address holding register 12 holds the logical address written immediately before the logical address is written to the logical address register 11. In the present embodiment, it is sufficient that at least only the upper part can be held. The comparison circuit 13 compares the upper part of the logical address held in each of the registers 11 and 12. The MMU 14 stores the logical address register 11
, Reads the upper part of the logical address, converts it to the upper part of the physical address, and outputs it. This output value is
Input to the selection circuit 15 and the conversion value register 16. The conversion value register 16 holds the upper part of the physical address output from the MMU 14 as a conversion value. Selection circuit 15
Selects and outputs one of the output value from the MMU 14 and the conversion value held in the conversion value register 16. This output value is written to the upper part of the physical address register 17.

In general, the MMU has an address conversion table for holding the upper part of the physical address in association with the upper part of the logical address.
The MU 14 is characterized in that the MU 14 is divided into a plurality of parts. FIG. 3 shows divided address conversion tables 18-1 to 18-4 divided into four, but the number of divisions is not limited to this. Hash circuit 1
Reference numeral 9 denotes only one divided address conversion table 1 based on the bit values constituting the upper part of the input logical address.
Select 8 The decoder 20 operates only the divided address conversion table 18 according to the output of the hash circuit 19. The selection circuit 21 is provided with the divided address conversion table 18
And selects and outputs the upper part of the physical address from one of them.

Next, the operation of this embodiment will be described. The previous logical address register 12 contains
It is assumed that the logical address written in the logical address register 11 in the immediately preceding fetch cycle is held.

In the current fetch cycle, the logical address to be converted is the logical address register 1
1 is written into the register 1
The upper part of the logical address stored in the storage unit 1 or 12 is compared. If the comparison result indicates that the values are not the same, the comparison circuit 13
Sends a mismatch signal (for example, 1) as a comparison result signal. When the comparison circuit 13 sends out a mismatch signal in this fetch cycle, the MMU 14 operates according to the mismatch signal. That is, in this fetch cycle, the MMU 14 reads the upper part of the logical address from the logical address register 11 and converts it to the upper part of the physical address. The upper part of the converted physical address is held in the conversion value register 16 and is sent to the selection circuit 15 at the same time. The details of the address conversion process in the MMU 14 will be described later.

The selection circuit 15 outputs the MMU 14 in this fetch cycle due to the input of the mismatch signal.
The upper part of the physical address output from is selected and output. This output value is written to the upper part of the physical address register 17. In the lower part of the physical address register 17, the lower part of the logical address held in the logical address register 11 is written as it is as the lower part of the physical address. As described above, the logical address written in the logical address register 11 is converted into a physical address.

On the other hand, the comparison circuit 13 includes the registers 11,
As a result of comparing the upper part of the logical address held in 12, if the values are the same, the comparison circuit 13 sends out a coincidence signal (for example, 0) as a comparison result signal. When the comparison circuit 13 sends a match signal in this fetch cycle, the MMU 14 does not operate. On the other hand, the selection circuit 15
Selects and outputs the conversion value held in the conversion value register 16 according to the coincidence signal. This output value is written to the upper part of the physical address register 17. In the lower part of the physical address register 17, the lower part of the logical address held in the logical address register 11 is written as it is as the lower part of the physical address. As described above, the logical address written in the logical address register 11 is converted into a physical address.

Thereafter, the logical address held in the logical address register 11 is written to the previous logical address register 12.

As described above, the current and previous logical addresses are compared, and if they match, the conversion value held in the conversion value register 16 is selected and output, thereby providing the MMU.
It is possible to obtain the upper part of the physical address without operating the device 14, and as a result, the physical address can be generated. That is, low power consumption can be achieved by not operating the MMU 14.

Next, M which is a feature of this embodiment
The operation of the MU 14 will be described in detail.

As described above, the MMU 14 operates according to the mismatch signal. The hash circuit 19 uses a hash function to hash all bit values constituting the upper part of the input logical address or a part thereof. As a result, the hash circuit 19 outputs the divided address conversion table 1
One of the items 8-1 to 18-4 is selected. The decoder 20 controls only the divided address conversion table 18 selected by the hash circuit 19 to operate. More specifically, since each of the divided address conversion tables 18 is formed of a memory element, the decoder 20 receives a selection result of the hash circuit 19, and receives a selection result of the selected divided address conversion table 18 from the selected line. A signal is output, and no signal is output from the other select lines. In the present embodiment, low power consumption is achieved by operating only the divided address conversion table 18 used in this manner. When the address conversion table is divided into four parts, the power consumption is reduced to one fourth by simple calculation.

The selection circuit 21 selects and outputs the upper part of the physical address output from the corresponding divided address conversion table 18 according to the selection result of the hash circuit 19.

According to the present embodiment, usually, a single address conversion table is divided into a plurality of parts, and when performing address conversion, only the corresponding divided address conversion table is operated, and the other is not operated. MMU14
The amount of power consumed by itself can be reduced. When the logical address for data is compared with the logical address for instructions,
Since it does not always change continuously, it is considered that the chance of carry increases. Therefore, when the address conversion target is data, the number of operations of the MMU 14 cannot be reduced. Therefore, while the first embodiment is a device suitable for address translation of instructions,
Since the power consumption of the MMU itself can be reduced, it can be said that the device is suitable for address conversion of data.

Embodiment 3 FIG. 4 is a conceptual diagram showing an information processing apparatus according to the present embodiment, which is an apparatus equipped with an address translator for translating a logical address into a physical address.

As described above, the address translation device shown in the first embodiment is suitable for address translation processing for an instruction logical address, and the address translation device shown in the second embodiment is suitable for a data logical address. Suitable for address translation processing. Therefore, it is intended to reduce the power consumption more effectively by adopting a configuration utilizing each feature.

That is, as shown in FIG. 4, the information processing apparatus according to the present embodiment is equipped with the address translator 1 described in the first embodiment for translating an instruction logical address, and is provided with a data logical address. The address translation device 10 shown in the second embodiment is mounted for the translation. The processor core unit 21 shown in FIG. 4 loads the corresponding program or the like into the physical memory 22 in order to use the program or data. At this time, if the load target is an instruction, the processor core unit 21 uses the address translation device 1. In the case of data, the address translation device 10 is used. This is more effective in reducing power consumption than using a single address translation device.

Embodiment 4 FIG. In the third embodiment, two types of address translation devices 1 and 10 are mounted.
Either one of the address translation devices 1 and 10 may be mounted. In particular, the address translator 10
Since the power consumption of U itself is reduced, as shown in FIG. 5, the power consumption is reduced even if the address translation device 10 converts not only the data but also the instruction logical address. be able to.

[0041]

According to the present invention, a carry signal output means is provided so that a carry signal is sent to the MMU and the physical address upper part selecting means. When the carry signal is not output, the MMU operates. Instead, the physical address is generated based on the converted value held in the logical address holding unit and the lower part of the logical address, so that the number of operations of the MMU can be reduced. This makes it possible to reduce the power consumption of the address translation device and the information processing device equipped with the address translation device.

Further, a divided address conversion table is formed by dividing the address conversion table of the MMU into a plurality of parts. When the MMU is operated, only the divided address conversion table used for the address conversion is operated. Since the operation is not performed, the power consumption of the MMU can be reduced.

Also, an address translator suitable for translating a logical address for an instruction and an address translator suitable for translating a logical address for a data are mounted on an information processing apparatus and used for an instruction and a data, respectively. Thus, power consumption can be reduced more effectively.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the address translator according to the present invention.

FIG. 3 is a diagram showing an internal configuration of an MMU according to a second embodiment.

FIG. 4 is a schematic block diagram showing a third embodiment of the information processing apparatus according to the present invention.

FIG. 5 is a schematic block diagram showing an information processing apparatus according to a fourth embodiment of the present invention.

[Explanation of symbols]

1,10 address converter, 2 address counter,
3,4 adder, 5 carry signal output circuit, 6,14 memory management unit (MMU), 7,15,2
1 selection circuit, 8, 16 conversion value register, 9, 17
Physical address register, 11 logical address registers,
12 previous logical address holding register, 13 comparison circuit, 18-1 to 18-4 divided address conversion table,
19 hash circuit, 20 decoder, 21 processor core unit, 22 physical memory.

Claims (4)

[Claims] An information processing apparatus for converting an upper part of a logical address into an upper part of a physical address, and generating a physical address from the upper part of the converted physical address and the lower part of the logical address. A logical address holding means in which logical addresses to be converted are sequentially written; and when the logical address is newly written or written to the logical address holding means, And a carry signal output means for outputting a carry signal when a carry from a portion to a higher order portion occurs, wherein the address conversion device outputs a carry signal from the carry signal output means. Only when the logical address is written to the logical address holding means, A memory management unit for converting to an upper part of an address, a conversion value holding unit for holding an output value from the memory management unit as a conversion value, and the memory management when a carry signal is output from the carry signal output unit. And a physical address upper part selecting means for selecting and outputting a converted value held in the converted value holding means at other times, the output value from the unit, and carry from the carry signal output means. An information processing apparatus, wherein a physical address is generated by using the converted value and a lower part of a logical address without operating the memory management unit when a signal is not output. 2. A memory management unit for converting an upper part of a logical address inputted as an address conversion target into an upper part of a physical address and outputting the same, wherein the upper part of the logical address is associated with the upper part of the physical address and held. And a table selecting means for selecting only one of the divided address conversion tables based on a bit value constituting the upper part of the input logical address. A memory management unit, comprising: operating only the divided address conversion table selected by the table selecting means when converting an input logical address into a higher order part. 3. An address translation device comprising the memory management unit according to claim 2. 4. The information processing apparatus according to claim 1, wherein said address translator is used for translating a logical address for instructions, and said address translator is further mounted for translating a logical address for data. apparatus.